Commit Graph

290 Commits

Author SHA1 Message Date
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
Ross Thompson
71a23626d5 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
Ross Thompson
59913e13aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
David Harris
e65fb5bb35 Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
Ross Thompson
f2c4df0a5b Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
Ross Thompson
8e48865140 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
Ross Thompson
8ae0a5bd7d relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ben Bracker
9709bd78e1 stop busybear from hanging 2021-07-02 17:22:09 -05:00
Ross Thompson
549b7b2a62 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
Ross Thompson
3dae02818c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
c3eaa3169e Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Ross Thompson
9d9415ea67 Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
4530e43df6 The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782 Page table walker now walks the table.
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
8dfbf60b67 AMO and LR/SC instructions now working correctly.
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Ross Thompson
9fd1761fd6 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
9927f771cc linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
Ross Thompson
d8183e59e4 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
bbracker
3d6b422e34 regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
409a73604c whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
b84419ff4e overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
David Harris
718630c378 Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
bbracker
56b0d4d016 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
bbracker
1f2a967e0f read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
6e9c6e3e6a whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
9469367da3 make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
52fb630379 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
3e32ba3684 make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
David Harris
43bc17350b Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
72f1e3eab6 buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
832e4fc7e3 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
3e11da2aa2 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Ross Thompson
6f58c66be8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4 Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2 Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
2021-06-04 13:49:33 -05:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396 Reorganized the icache names. 2021-06-04 12:53:42 -05:00
David Harris
a61411995a moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
bbracker
8338b3bd34 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
28abd28b1f fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00