Katherine Parry
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acdd2e4504
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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Katherine Parry
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0cc07fda1b
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
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Ross Thompson
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71a23626d5
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Fixed bug in the LSU pagetable walker interlock.
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2021-07-06 10:41:36 -05:00 |
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Ross Thompson
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59913e13aa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-05 16:07:27 -05:00 |
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David Harris
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e65fb5bb35
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Added F_SUPPORTED flag to disable floating point unit when not in MISA
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2021-07-05 10:30:46 -04:00 |
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Ross Thompson
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f2c4df0a5b
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Removed the TranslationVAdrQ as it is not necessary.
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2021-07-04 16:49:34 -05:00 |
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Ross Thompson
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8e48865140
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-04 16:19:39 -05:00 |
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Ross Thompson
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8ae0a5bd7d
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relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
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2021-07-04 13:49:38 -05:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ben Bracker
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9709bd78e1
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stop busybear from hanging
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2021-07-02 17:22:09 -05:00 |
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Ross Thompson
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549b7b2a62
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Merge branch 'main' into bigbadbranch
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2021-07-02 11:52:26 -05:00 |
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Ross Thompson
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3dae02818c
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OMG. It's working!
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2021-07-01 17:37:53 -05:00 |
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Ross Thompson
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c3eaa3169e
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Fixed the wrong virtual address write into the dtlb.
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2021-07-01 16:55:16 -05:00 |
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Ross Thompson
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9d9415ea67
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Got some stores working in virtual memory.
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2021-07-01 12:49:09 -05:00 |
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Ross Thompson
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4530e43df6
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The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
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2021-06-30 17:02:36 -05:00 |
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Ross Thompson
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07a0b66fdf
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Major rewrite of ptw to remove combo loop.
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2021-06-30 16:25:03 -05:00 |
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Ross Thompson
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b31e0afc2a
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The icache now correctly interlocks with the PTW on TLB miss.
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2021-06-30 11:24:26 -05:00 |
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Ross Thompson
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2598f08782
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Page table walker now walks the table.
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
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2021-06-29 22:33:57 -05:00 |
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Ross Thompson
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ae6140bd94
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Don't use this branch walker still broken.
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2021-06-28 17:26:11 -05:00 |
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Ross Thompson
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8dfbf60b67
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AMO and LR/SC instructions now working correctly.
Page table walking is not working.
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2021-06-25 15:42:07 -05:00 |
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Ross Thompson
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9fd1761fd6
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Working through a combo loop.
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2021-06-25 14:49:27 -05:00 |
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Ross Thompson
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17636b3293
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Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
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2021-06-25 11:05:17 -05:00 |
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bbracker
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9927f771cc
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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Ross Thompson
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d8183e59e4
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Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
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2021-06-24 14:42:59 -05:00 |
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bbracker
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3d6b422e34
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regression can overcome the fact that buildroots UART prints stuff
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2021-06-24 02:00:01 -04:00 |
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bbracker
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409a73604c
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whoops meant to remove notifications from busybear, not buildroot
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2021-06-24 01:54:46 -04:00 |
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bbracker
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b84419ff4e
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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David Harris
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718630c378
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Reduced complexity of pmpadrdec
|
2021-06-23 03:03:52 -04:00 |
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bbracker
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56b0d4d016
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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bbracker
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1f2a967e0f
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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6e9c6e3e6a
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whoops wavedo typo
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2021-06-20 05:36:54 -04:00 |
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bbracker
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9469367da3
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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52fb630379
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remove lingering busybear stuff from buildroot do files
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2021-06-20 00:50:53 -04:00 |
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bbracker
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3e32ba3684
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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David Harris
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43bc17350b
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Restored wally-busybear testbench now that graphical sim is working
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2021-06-18 12:36:25 -04:00 |
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bbracker
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72f1e3eab6
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buildroot added to regression because it passes regression
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2021-06-18 09:49:30 -04:00 |
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David Harris
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e03912f64c
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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832e4fc7e3
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making linux waveforms more useful
|
2021-06-17 08:37:37 -04:00 |
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bbracker
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3e11da2aa2
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temporarily removing buildroot from regression until it is regenerated
|
2021-06-07 13:20:50 -04:00 |
|
David Harris
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95cc70295b
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Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
|
David Harris
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8bbabb683d
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Refactored configuration files and renamed testbench-busybear to testbench-linux
|
2021-06-07 09:46:52 -04:00 |
|
Ross Thompson
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6f58c66be8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-06-04 15:16:39 -05:00 |
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Ross Thompson
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e200b4b5a4
|
Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
|
2021-06-04 15:14:05 -05:00 |
|
Ross Thompson
|
35afdecda2
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Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
|
2021-06-04 13:49:33 -05:00 |
|
Katherine Parry
|
19116ed889
|
Double-precision FMA instructions
|
2021-06-04 14:00:11 -04:00 |
|
Ross Thompson
|
2c16591396
|
Reorganized the icache names.
|
2021-06-04 12:53:42 -05:00 |
|
David Harris
|
a61411995a
|
moved shared constants to a shared directory
|
2021-06-03 22:41:30 -04:00 |
|
bbracker
|
8338b3bd34
|
expanded GPIO testing and caught small GPIO bug
|
2021-06-03 10:03:09 -04:00 |
|
bbracker
|
28abd28b1f
|
fixed InstrValid signals and implemented less costly MEPC loading
|
2021-06-02 10:03:19 -04:00 |
|
bbracker
|
a45b61ede9
|
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
|
2021-05-28 23:11:37 -04:00 |
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