Katherine Parry
cd53ae67d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
David Harris
d73645944f
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
6baded9121
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
254ebf478e
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
slmnemo
98c07ce2c0
Added more comments
2022-06-13 12:26:08 -07:00
slmnemo
3d715a098c
Added comment about name of LSUBusInit/Lock signal
2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68
Added comments to signals added so the bus is easier to analyze
2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b
Fixed failed regression state by only enabling counting when doing cached operations
2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
2022-06-10 19:10:01 -07:00
slmnemo
dc11066ff2
Passed Regression: Seems to work perfectly fine
2022-06-09 18:21:13 -07:00
slmnemo
5a6eae214a
?
2022-06-09 17:50:47 -07:00
slmnemo
3e8d3bae88
Changes made on 9th Jun
2022-06-09 17:33:51 -07:00
slmnemo
0d04751c77
Fixed error when doing uncached accesses where HTRANS was always 2
2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
2022-06-08 17:34:02 -07:00
slmnemo
315c2f0669
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
284e0395a0
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
6d36150c3d
Fixed off-by-one error in busdp capture
2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
c7ec9282fe
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
446ad498aa
Fixed double assignment on LSUBurstType
2022-06-01 01:04:49 +00:00
slmnemo
bc17f883d4
changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word
2022-05-26 18:41:27 -07:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80fc716cd7
Added signal to monitor HBURST and comments for each burst in busdp
2022-05-26 13:35:49 -07:00
slmnemo
08430a1e85
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
5670f77de2
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
e2e63ca9a8
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
04fd22aeb0
endian swapper
2022-05-08 06:51:50 +00:00
David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
22842816a8
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
c07b9d1722
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
David Harris
d8b4c985cd
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
Ross Thompson
bfc68bef69
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
e4f4e1bd43
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-30 11:09:44 -05:00
Ross Thompson
839bede656
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
2022-03-30 11:04:15 -05:00
David Harris
c4f2c6b110
fpu compare simplification, minor cleanup
2022-03-29 17:11:28 +00:00
Ross Thompson
fe896bff8e
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
71aad2d213
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
8f74fd2a50
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-23 14:10:38 -05:00
Ross Thompson
b2487f4b72
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-22 21:28:50 -05:00
Ross Thompson
ca8fb45367
Added comment about needed fix to misaligned fault.
2022-03-22 16:52:07 -05:00
Ross Thompson
ee4b38dce3
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
86cc758354
cleanup of ram.sv
2022-03-11 18:09:22 -06:00
Ross Thompson
67ff8f27f4
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
b7a680ec2a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847
atomic cleanup.
2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df
Name changes.
2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
1aa87c9f3a
Moved subwordwrite to lsu directory.
2022-03-10 18:15:25 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
Ross Thompson
95bb4cc8a8
Minor cleanup to interlockfsm.
2022-03-08 23:38:58 -06:00
Ross Thompson
0310fe858f
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
Ross Thompson
3ec32d7ce8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
David Harris
2cea3349ad
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
971dd494f6
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
bd7343b791
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
f716cce832
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
36ab78ef3b
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
8a2ee22395
Finished merge.
2022-02-08 11:36:24 -06:00
David Harris
c61cd55c5c
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
Ross Thompson
ea84211ff9
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
011ad09341
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
4074f695e0
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
40eb055861
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
Ross Thompson
290430cda8
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
David Harris
38bbe23d14
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
