Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Moved the hwdata mux back into the busdp.

Browse Source
This commit is contained in:
Ross Thompson 2022-02-04 22:39:13 -06:00
parent 40eb055861
commit 4074f695e0
3 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/ifu/ifu.sv
View File

@ -193,7 +193,7 @@ module ifu (
.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(),
.LSUBusRead(IFUBusRead), .LSUBusSize(),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.WordCount(), .SelUncachedAdr(),
.WordCount(), .SelUncachedAdr(), .LSUBusHWDATA(),
.ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine),
.DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
.DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),

9
pipelined/src/lsu/busdp.sv
View File

@ -34,7 +34,7 @@
`include "wally-config.vh"
module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL)
module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL, LSU=0)
(
input logic clk, reset,
// bus interface
@ -42,7 +42,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL)
input logic LSUBusAck,
output logic LSUBusWrite,
output logic LSUBusRead,
// output logic [`XLEN-1:0] LSUBusHWDATA,
output logic [`XLEN-1:0] LSUBusHWDATA,
output logic [2:0] LSUBusSize,
input logic [2:0] LSUFunct3M,
output logic [`PA_BITS-1:0] LSUBusAdr,
@ -85,6 +85,11 @@ module busdp #(parameter WORDSPERLINE, LINELEN, WORDLEN, LOGWPL)
mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr);
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
//assign PreLSUBusHWDATA = ReadDataWordM;// ReadDataLineSetsM[WordCount]; // only in lsu, not ifu
// this mux is only used in the LSU's bus.
if(LSU == 1) mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalAMOWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA));
else assign LSUBusHWDATA = '0;
mux2 #(3) lsubussizemux(
.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize));
mux2 #(WORDLEN) UnCachedDataMux(

8
pipelined/src/lsu/lsu.sv
View File

@ -199,10 +199,10 @@ module lsu (
logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0];
logic [`PA_BITS-1-`XLEN/8-LOGWPL:0] Pad;
busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL) busdp(
busdp #(WORDSPERLINE, LINELEN, `XLEN, LOGWPL, 1) busdp(
.clk, .reset,
.LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
.WordCount, .SelUncachedAdr,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize,
.WordCount, .SelUncachedAdr,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM,
.ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
@ -210,8 +210,6 @@ module lsu (
assign Pad = '0;
assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM;
mux2 #(`XLEN) lsubushwdatamux(
.d0(ReadDataWordM), .d1(FinalAMOWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA));
subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread(