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234 Commits 4 Branches 2 Tags 53 MiB
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234 Commits

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Author SHA1 Message Date
Noah Boorstin
b6dc0a8707 busybear: only check pc when it actually changes 2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
Noah Boorstin
141f6a5496 Merge branch 'main' into busybear 2021-02-28 20:48:23 +00:00
Noah Boorstin
a5f1dbfe23 add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00
Noah Boorstin
a267115635 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
932bc0ef85 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Noah Boorstin
856a1079cc busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
Noah Boorstin
2769b147cb busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489 busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
0596d61a2a busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
e8b306bcba merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
4c7b185d90 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
kaveh Pezeshki
2782ca2480 fixed sensitivity list on error checking always block, removed useless once and for all 2021-02-26 13:41:16 -05:00
kaveh pezeshki
adadc21fc6 restored 2021-02-26 02:22:08 -08:00
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
Brett Mathis
87e4311339 Fcmp/Fsgn pipeline modules 2021-02-25 18:22:30 -06:00
David Harris
bad180fc15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2 Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
Teo Ene
b9701293a0 Changed TIMBASE in coremark config file 2021-02-25 11:03:41 -06:00
Teo Ene
a6c16af721 Merge remote-tracking branch 'origin/lab3' into main 2021-02-25 10:28:20 -06:00
Teo Ene
8491deb1a9 Changed .do file back to run all 2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
eb52fd1c5a removed WALLY ALU tests to avoid merge conflict with main branch 2021-02-25 00:15:22 -05:00
Teo Ene
cfd45a46c3 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb condensed always blocks to avoid race conditions 2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe added comments for RAM and bootram, removed trailing whitepace 2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec busybear: add bootram section in the same manner as ram 2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8 busybear: add support for subwords in ram 
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
 2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b busybear: start adding ram 2021-02-23 22:01:23 +00:00
Katherine Parry
07641203ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
906ec30339 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
5394d38e4a busybear: remove unused signals 2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
7737b0f709 Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Thomas Fleming
ca51e7ca1c Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
87ad559a90 Updated creation date of mul 2021-02-18 08:13:08 -05:00
David Harris
fe7299c155 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00