David Harris
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e67f125201
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Header comments
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2023-01-12 04:35:44 -08:00 |
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David Harris
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7d93659f6b
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changed name to CORE-V-WALLY
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2023-01-11 15:15:08 -08:00 |
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David Harris
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b911056e66
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Changed Wally to CORE-V Wally
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2023-01-11 14:03:44 -08:00 |
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David Harris
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e92cffbb5e
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Changed MIT license to Solderpad License
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2023-01-10 11:35:20 -08:00 |
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David Harris
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15b829bbf7
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Removed unused signals
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2023-01-07 06:06:54 -08:00 |
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Ross Thompson
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e34f80db2f
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More branch predictor cleanup.
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2023-01-05 17:19:27 -06:00 |
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Ross Thompson
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8ca6c1255e
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More branch predictor cleanup.
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2023-01-05 13:36:51 -06:00 |
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Ross Thompson
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b14b71c7a9
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Fixed bug with the performance counters not updating.
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2022-12-24 14:24:17 -06:00 |
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Ross Thompson
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b5a85b55f1
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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David Harris
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1f6dc62bb3
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Moved InstrValidNotFLushed to csr including InstrValidM
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2022-12-23 00:27:44 -08:00 |
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David Harris
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85d0b697bf
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Removed unused StallW from CSRs
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2022-12-23 00:21:36 -08:00 |
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David Harris
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93bb8036be
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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51b92285d3
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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David Harris
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567f76c2a5
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Code cleanup
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2022-12-22 10:04:50 -08:00 |
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David Harris
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3562542728
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comment cleanup
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2022-12-21 12:39:09 -08:00 |
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David Harris
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ca949f2110
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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Ross Thompson
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f6393d1288
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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c41d58bd29
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Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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David Harris
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28085ce8eb
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Clean up vecgtored interrupts
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2022-12-20 16:53:09 -08:00 |
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David Harris
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88ee834c97
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Converted tvecmux to structural
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2022-12-20 16:24:04 -08:00 |
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Ross Thompson
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2f0d20b8b0
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privileged pc mux cleanup.
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2022-12-20 18:05:44 -06:00 |
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Ross Thompson
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cba2ed64e5
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Moved privileged pc logic into privileged unit.
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2022-12-20 17:55:45 -06:00 |
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Ross Thompson
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ef4ecbe62b
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Changed long names of vectored pcm signals.
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2022-12-20 17:01:20 -06:00 |
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David Harris
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0c10ec942a
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Replaced || and && with single ops
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2022-12-20 01:33:35 -08:00 |
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David Harris
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940fd2f924
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Clean up interrupt masking by Commit
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2022-12-16 08:27:39 -08:00 |
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Ross Thompson
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fbf543bf57
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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0ed0c18aa1
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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32449dfe97
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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David Harris
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05aa18fe14
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Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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129fab3794
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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David Harris
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31815422d2
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../src/privileged/csrc.sv
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2022-05-31 21:12:17 +00:00 |
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David Harris
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2935188035
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Moved delegation logic from privmode to trap to simplify interface
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2022-05-31 14:58:11 +00:00 |
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Ross Thompson
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9079e67aae
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Updated fpga debugger.
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2022-05-17 23:04:01 -05:00 |
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David Harris
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f5e2cff45a
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Cause simplification
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2022-05-12 23:47:21 +00:00 |
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David Harris
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6303d4e81f
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Cause simplification
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2022-05-12 23:39:10 +00:00 |
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David Harris
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c4621c5b6b
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Cause simplification
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2022-05-12 23:37:40 +00:00 |
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David Harris
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7daf631c13
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Cause simplification
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2022-05-12 23:33:35 +00:00 |
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David Harris
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de51c7eeb3
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Cause simplification
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2022-05-12 23:33:22 +00:00 |
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David Harris
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803bfc4fe4
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Cause simplification
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2022-05-12 23:29:35 +00:00 |
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David Harris
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2d27d20db9
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Cause simplification
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2022-05-12 23:27:02 +00:00 |
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David Harris
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87dadc8208
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trap/csr cleanup
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2022-05-12 22:26:21 +00:00 |
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David Harris
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ea0d9fd9a8
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More trap/csr simplification
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2022-05-12 22:06:03 +00:00 |
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David Harris
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2eb6a65fa2
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More trap/csr simplification
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2022-05-12 22:04:20 +00:00 |
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David Harris
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2d8ccbd4ea
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More trap/csr simplification
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2022-05-12 22:00:23 +00:00 |
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David Harris
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417e36bff5
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More trap/csr simplification
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2022-05-12 21:55:50 +00:00 |
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David Harris
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ca6b7716e2
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Simplifying trap/csr interface
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2022-05-12 21:50:15 +00:00 |
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David Harris
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56c154f2e7
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Simplified MTVAL logic
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2022-05-12 21:36:13 +00:00 |
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David Harris
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730bcac6ba
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Partitioned privileged pipeline registers into module
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2022-05-12 20:45:45 +00:00 |
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David Harris
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c5868b81e4
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privileged cleanup
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2022-05-12 20:21:33 +00:00 |
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David Harris
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5537c33196
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Formatting cleanup
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2022-05-12 18:37:47 +00:00 |
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