cvw/pipelined/src/privileged
2022-05-12 21:50:15 +00:00
..
csr.sv Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
csrc.sv Clean up unused signals 2022-05-12 14:49:58 +00:00
csri.sv Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
csrm.sv Fixed typo in csrm 2022-05-12 06:55:39 -07:00
csrs.sv Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
csrsr.sv Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
csru.sv Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
privdec.sv Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
privileged.sv Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
privmode.sv Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
privpiperegs.sv Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
trap.sv Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00