8871 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
David Harris	af4403342f	renamed run_vcs.py to run_vcs, added instr/data in ebu	2024-07-03 08:02:38 -07:00
David Harris	a2fb6a21c5	Removed testbench-imperas now that wsim supports lockstep and single ELF files	2024-07-03 06:25:32 -07:00
David Harris	1b62d2116a	VCS lockstep working	2024-07-02 18:05:13 -07:00
David Harris	aff0ad9c02	Progress on VCS; run_vcs rewritten in Python to ease passing parameters	2024-07-02 14:23:34 -07:00
David Harris	e72c8b8e09	Watchdog timeout on buildroot boot is a halting criteria	2024-07-02 14:22:51 -07:00
David Harris	a0729d074b	regression --nightly --buildroot runs buildroot boot in Verilator all the way to login prompt and checks success	2024-07-02 14:20:40 -07:00
David Harris	38b0c10f9b	Updated wallyTracer to be compatible with VCS	2024-07-02 04:47:53 -07:00
David Harris	68a105d5d8	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-29 05:35:46 -07:00
Jordan Carlin	b0f5fbe497	Merge pull request #861 from stineje/main ... Temporarily removing Q tests as not everyone has tests	2024-06-28 12:54:18 -07:00
James Stine	f660779ba9	Fix for Q causing it to error out - commented out line for ISA and reset-val so can be put back	2024-06-28 12:17:15 -05:00
James Stine	8bb08fefe7	add three programs to APT to make sure they are there for new installs	2024-06-28 12:16:08 -05:00
David Harris	c972a914c8	Removed +plusarg_save because it doesn't silence VCS	2024-06-28 07:48:01 -07:00
David Harris	4a3532bf5a	VCS lockstep progress	2024-06-28 07:19:03 -07:00
David Harris	6cf250821d	Added VCS +plusarg_save to silence compiler	2024-06-28 06:53:44 -07:00
David Harris	e795143983	Turned off debug access to speed up VCS	2024-06-28 06:43:14 -07:00
David Harris	29c94e8abb	Regression fully running with Verilator, which is now the default and much faster than the others	2024-06-28 06:17:40 -07:00
David Harris	31b54fb247	Progress on VCS lockstep	2024-06-27 11:16:17 -07:00
David Harris	d933c80c55	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-27 07:07:08 -07:00
David Harris	4d87de2600	Merge pull request #855 from jordancarlin/derivgen_fix ... FPU without privilege modes + derived config fixes	2024-06-27 07:06:33 -07:00
Jordan Carlin	e7d4a2ee81	Trim down no priv regression tests	2024-06-27 07:01:55 -07:00
David Harris	bf9fdcf9f9	Cleaned up lint errors in testbench_fp; still not working in Verilator because readvectors receives the wrong unit, fmt, opctrl	2024-06-27 04:26:56 -07:00
David Harris	f12cdf55fe	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-27 03:22:55 -07:00
David Harris	2845d7eab1	Merge pull request #856 from jordancarlin/testbench_cleanup ... Testbench cleanup	2024-06-27 03:21:53 -07:00
Jordan Carlin	784151e165	Fix testbench_fp to use F_SUPPORTED, not S_SUPPORTED	2024-06-26 22:29:00 -07:00
Jordan Carlin	032de34dbd	Lint fixes for no priv mode configs	2024-06-26 22:15:18 -07:00
Jordan Carlin	47e67e99ff	Add no priv mode tests to regression	2024-06-26 22:00:29 -07:00
Jordan Carlin	c3cb4e5d1c	Fix FPU without S_SUPPORTED - #840	2024-06-26 22:00:29 -07:00
Jordan Carlin	607a09ca62	Add derived configs without privilege modes	2024-06-26 21:59:53 -07:00
Jordan Carlin	d3bb39d918	Fix derived configs with D_SUPPORTED = 0	2024-06-26 21:25:59 -07:00
Jordan Carlin	221f710baf	Use QUESTA as flag for	2024-06-26 21:18:40 -07:00
David Harris	8fe2052b1f	Fix derived configuration with new derivgen script	2024-06-26 16:09:59 -07:00
David Harris	21e5fa3103	Merge pull request #854 from Shreesh-Kulkarni/main ... Files for Quad Precision Testing Support for Wally	2024-06-26 11:41:26 -07:00
Shreesh-Kulkarni	93fb0f2a84	Files for Quad Precision Testing Support for Wally	2024-06-26 11:36:04 -07:00
David Harris	a013c7083f	Merge pull request #853 from jordancarlin/derivgen_fix ... Fix derivgen	2024-06-26 08:31:22 -07:00
Jordan Carlin	1a1da9b2c4	Update derivlist.txt based on exact matching	2024-06-26 07:49:27 -07:00
Jordan Carlin	0da6e35988	Fix derivgen.pl to find exact keys	2024-06-26 07:45:04 -07:00
Jordan Carlin	f003f8fae9	Merge pull request #852 from davidharrishmc/dev ... Clean up unused signals for derived configurations	2024-06-26 07:34:00 -07:00
David Harris	0fcc7878dc	Updated march lists	2024-06-25 21:54:58 -07:00
Jordan Carlin	b76941d278	Use VCS built-in default macro instead of defining SIM_VCS	2024-06-21 15:17:59 -07:00
Rose Thompson	e1fc44a5bf	Merge pull request #849 from davidharrishmc/dev ... lint cleanup and divider optimization	2024-06-20 09:04:19 -07:00
David Harris	486e6ff0f6	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-20 08:43:48 -07:00
David Harris	d8d94eeafa	Merge pull request #808 from jordancarlin/main ... Update riscv-arch-test	2024-06-20 08:43:41 -07:00
Jordan Carlin	90f5a4ef48	Only run fmsub_b15 for f_fma test	2024-06-20 07:48:33 -07:00
David Harris	25780f53ce	Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.	2024-06-20 00:57:58 -07:00
David Harris	27457f4ef4	Merge pull request #848 from ross144/main ... Covergen doesn't produce stores and riscv-dv only generates tests	2024-06-20 00:10:33 -07:00
David Harris	0ab3f28991	Lint cleanup	2024-06-20 00:10:03 -07:00
Ross Thompson	e88a2f7eaa	Merge branch 'main' of github.com:ross144/cvw into main	2024-06-19 15:14:28 -07:00
Ross Thompson	9e93f21990	Updated covergen to not include stores as they are incomplete. ... Modified makefile riscv-dv to not simulation only generate tests.	2024-06-19 15:13:49 -07:00
David Harris	5f1ee1ac85	Fixed undriven signal in certain config	2024-06-19 15:12:35 -07:00
David Harris	e4febf25ae	Merge pull request #847 from ross144/main ... Partial fix for verilator +args. At least compiles.	2024-06-19 14:27:39 -07:00