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Author	SHA1	Message	Date
Ross Thompson	af28cfb70c	Added SDC defines to each config mode. ... Added sd_top which is the sd card reader.	2021-09-24 12:24:30 -05:00
Ross Thompson	0a33f5fa46	setup so the sdc does not need to load a model in the imperas test bench.	2021-09-24 11:30:52 -05:00
Ross Thompson	78028947bf	Updated Imperas test bench to work with the SDC reader.	2021-09-24 11:22:54 -05:00
Ross Thompson	4256ef82b1	SDC to ABHLite interface partially done. ... Added SDC to adrdec and uncore.	2021-09-24 10:45:09 -05:00
Ross Thompson	a182263b1c	Added clock gater and divider to generate the SDCCLK.	2021-09-23 17:58:50 -05:00
Ross Thompson	9ed7a1f494	Partial implementation of SDC AHBLite interface.	2021-09-23 17:45:45 -05:00
Ross Thompson	0f7be5e591	Started the AHBLite to SDC interface.	2021-09-22 18:08:38 -05:00
Ross Thompson	f5905f33d3	Initial SD Card reader.	2021-09-22 10:50:29 -05:00
Ross Thompson	d09b381183	Fixed the amo on dcache miss cpu stall issue.	2021-09-17 22:15:03 -05:00
Ross Thompson	99d675b872	Finished adding the d cache flush. Required ensuring the write data, address, and size are ... correct when transmitting to AHBLite interface.	2021-09-17 13:03:04 -05:00
Ross Thompson	8fa287a449	The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.	2021-09-17 10:33:57 -05:00
Ross Thompson	b92070a67a	Updated Dcache to fully support flush. This appears to work. ... Updated PCNextF so it points to the correct PC after icache invalidate. Build root crashes with PCW mismatch and invalid register writes.	2021-09-17 10:25:21 -05:00
Ross Thompson	d4398c23fb	Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.	2021-09-16 18:32:29 -05:00
Ross Thompson	55cbd957f0	Added counters to walk through d cache flush.	2021-09-16 17:12:51 -05:00
Ross Thompson	4ca0c0ea7d	Added flush controls to cachway.	2021-09-16 16:56:48 -05:00
Ross Thompson	eb7b5f1d63	Added invalidate to icache.	2021-09-16 16:15:54 -05:00
bbracker	92ddc9b20a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-09-15 17:31:11 -04:00
bbracker	b1be8f4858	fix regression	2021-09-15 17:30:59 -04:00
David Harris	72c1cc33f5	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
bbracker	f94a13e242	created script to determine which functions are most frequently used	2021-09-14 19:41:05 -04:00
bbracker	255d69e697	IRQ timing template	2021-09-13 18:48:28 -04:00
David Harris	e32ab128e9	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-09-13 12:41:07 -04:00
David Harris	654f3d1940	Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64	2021-09-13 12:40:40 -04:00
Ross Thompson	d4c87d17b2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-09-13 09:41:34 -05:00
David Harris	1847198da9	Cleaned up wally-arch test scripts	2021-09-13 00:02:32 -04:00
David Harris	b2fe8eddc0	Restored old integer divider	2021-09-12 22:07:52 -04:00
Ross Thompson	144003cb41	FPGA test bench and test program.	2021-09-12 20:41:54 -05:00
David Harris	1f6e4c71fc	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
Ross Thompson	225657b8f9	Fixed bug with or_rows. ... If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.	2021-09-11 15:51:11 -05:00
Ross Thompson	3b12235954	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
Ross Thompson	3ff8d0095d	Fixed dcache to prevent latches in FPGA synthesized design.	2021-09-11 12:03:48 -05:00
Ross Thompson	29efd1d222	Third attempt at fixing the write enables for the icache cacheway.	2021-09-09 15:08:10 -05:00
Ross Thompson	230c794edd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Refixed some bit width issues in the icache.	2021-09-09 12:44:02 -05:00
Ross Thompson	90f2821bea	fixed some lint bugs.	2021-09-09 12:38:57 -05:00
bbracker	886e8125db	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-09-09 13:22:31 -04:00
bbracker	83520aeb42	changed fix_mem to not use hardcoded file names	2021-09-09 13:22:24 -04:00
David Harris	cb624fe679	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
David Harris	a31828e925	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-09-08 16:00:12 -04:00
David Harris	30e2ec3987	Added testbench-arch for riscv-arch-test suite	2021-09-08 15:59:40 -04:00
Ross Thompson	8141a515bb	Changed configs to support 4 ways set associative caches.	2021-09-08 12:52:49 -05:00
Ross Thompson	6606eea27e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-09-08 12:47:03 -05:00
Ross Thompson	5bc90ef32f	Slight modification to wave file.	2021-09-08 10:40:46 -05:00
bbracker	5e9a39e755	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00
bbracker	b3f00f2682	make testbench successfully deactivate TimerIntM so as to create a nice pulse	2021-09-07 15:36:47 -04:00
Ross Thompson	150a73d6cf	Set associate icache working, but way 0 is never written.	2021-09-07 12:46:16 -05:00
bbracker	28fed18421	No longer forcing CSRReadValM because that can feedback to corrupt some CSRs	2021-09-06 22:59:54 -04:00
Ross Thompson	00f50184d8	Changed name of memory in icache.	2021-09-06 20:54:52 -05:00
bbracker	0646bf2b90	help in case a script is run accidentally	2021-09-06 16:23:45 -04:00
bbracker	a13b561759	modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)	2021-09-04 19:49:26 -04:00
bbracker	58d478eb23	restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair	2021-09-04 19:45:04 -04:00