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1070 Commits

Author SHA1 Message Date
Katherine Parry
531829f7c8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-19 23:44:41 +00:00
Katherine Parry
afcddf7035 oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
Daniel Torres
d33d0d22bd commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
4c2afbbc4f moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
a590728350 reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
David Harris
59eb11b73a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 23:11:12 +00:00
Katherine Parry
e599f82b29 moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
921debf930 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
ea7b32a50b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 17:31:29 +00:00
Katherine Parry
5bb1478859 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
David Harris
7c744f0053 Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
David Harris
6e1d4ec4ed restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
Katherine Parry
a4cd157f00 forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
e498d87c5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-15 20:17:08 +00:00
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
cturek
ec9536f983 Square root radix 2 working, does not work with division 2022-07-14 22:52:09 +00:00
cturek
9f18f6a203 Square root 2022-07-14 21:19:45 +00:00
cturek
38bbd19abf Six tests passing and a bunch of sizizing issues fixed 2022-07-14 19:38:27 +00:00
Katherine Parry
a0e9e93d4f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-14 18:16:13 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
cturek
f49c2a969f S and SM are updating but are not correct yet 2022-07-14 00:39:30 +00:00
Katherine Parry
e5a8ac2a44 renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
cturek
7629173b15 DIVLEN and counter updated for sqrt computation and rounding 2022-07-13 22:42:39 +00:00
Katherine Parry
7e163e22a3 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
77ea4e47cb removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
cturek
d57fb6f98a radix 4 files removed from srt and divlen modified for sqrt 2022-07-13 19:46:48 +00:00
cturek
9b7e63f482 Lint error fixed and added comments to preprocessing 2022-07-13 19:34:04 +00:00
cturek
81f396f885 Testbench accepts standard test vector files 2022-07-13 18:30:18 +00:00
cturek
11bb3f0a3e Test generation files in common format 2022-07-13 18:11:13 +00:00
cturek
110b762b55 Finalized sqrt, ready for debugging 2022-07-13 17:56:23 +00:00
cturek
31db938e7e Added adder input selection to on the fly converter 2022-07-13 17:47:27 +00:00
cturek
bb7e73abf0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-13 17:36:56 +00:00
Katherine Parry
26e39dd325 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
cturek
5c9f011561 little fix 2022-07-12 23:04:33 +00:00
cturek
ed9106128f Square root implemented 2022-07-12 22:45:54 +00:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
cturek
9d4acc9ddb C register and other various fixes 2022-07-12 22:18:56 +00:00
cturek
3483b92480 On the fly conversion for square root 2022-07-12 02:21:38 +00:00
Katherine Parry
5c0ecfa433 forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
DTowersM
191c7a2ee3 added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
cturek
2dc074ea93 F Selection 2022-07-08 21:53:52 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
d10ad0e883 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
David Harris
c72e4d43d2 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
905b7ffc84 moved unsused division code again 2022-07-07 16:41:26 -07:00
cturek
b7e590ebb0 Sqrt exponents 2022-07-07 23:34:56 +00:00
Katherine Parry
5751d86f69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-07 16:29:44 -07:00
Katherine Parry
2bbde827e6 Revert "moved old divsqrt to unusedsrc" 
This reverts commit c9f5ae12ea.
 2022-07-07 16:29:17 -07:00
DTowersM
5a68ff9afb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-07 23:11:35 +00:00
DTowersM
d55833e4f3 new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory 2022-07-07 23:11:02 +00:00
Katherine Parry
c9f5ae12ea moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
cturek
b41a6f069b Seventeen Square Root Tests 2022-07-07 22:48:46 +00:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
cturek
89e17b6f3c Preprocessing for square root 2022-07-07 21:23:30 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
b7462ed6ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 15:51:33 +00:00
slmnemo
c5fd98ba99 sim-buildroot-batch now runs wally-pipelined-batch 
with option buildroot buildroot-no-trace to boot linux from step 0
 2022-07-06 18:06:43 -07:00
David Harris
6a030fc2a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:44:47 +00:00
DTowersM
47a990d9f1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-06 23:44:27 +00:00
DTowersM
1e8ccf3449 added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu 2022-07-06 23:43:57 +00:00
David Harris
08ae2db080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
cb33d2289b fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
9ef38145d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
a599084b88 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
846f12aa2e new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
01e6d69a67 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
cturek
e7ac99a683 Radix 2 Integer division working (without signs or remainder) 2022-07-05 21:34:49 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
d033659beb Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
e7fe7ad0c8 AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
4723ff559c Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
aa3dc8bfe1 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
4c48d71e4b removed delay in ahblite 2022-07-05 04:59:28 +00:00
David Harris
dab87811e9 Removed sig4 spurious message from testbench 2022-07-05 03:27:14 +00:00
David Harris
2b3038edf8 Added check to halt testbench on failing to find file 2022-07-05 02:28:59 +00:00
Katherine Parry
010a05f583 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00