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Square root implemented

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This commit is contained in:
cturek 2022-07-12 22:45:54 +00:00
parent 452b017f9a
commit ed9106128f
2 changed files with 6 additions and 6 deletions
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8
pipelined/srt/srt.sv
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@ -92,10 +92,10 @@ module srt (
csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
// If only implementing division, use divide otfc
// otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
// otherwise use sotfc
creg sotfcC(clk, Start, C);
sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot);
// creg sotfcC(clk, Start, C);
// sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot);
expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
@ -272,7 +272,7 @@ module sotfc2(
flopr #(`DIVLEN+4) Sreg(clk, Start, SMNext, SM);
mux2 #(`DIVLEN+4) Smux(SNext, {4'b0001, (`DIVLEN){1'b0}}, Start, SMux);
flop #(`DIVLEN+4) SMreg(clk, SMux, M);
flop #(`DIVLEN+4) SMreg(clk, SMux, S);
always_comb begin
if (sp) begin

4
pipelined/srt/testbench.sv
View File

@ -82,7 +82,7 @@ module testbench;
// Equip Int test or Sqrt test
assign Int = 1'b0;
assign Sqrt = 1'b1;
assign Sqrt = 1'b0;
// Divider
srt srt(.clk, .Start(req),
@ -111,7 +111,7 @@ module testbench;
begin
testnum = 0;
errors = 0;
$readmemh ("sqrttestvectors", Tests);
$readmemh ("testvectors", Tests);
Vec = Tests[testnum];
a = Vec[`mema];
{asign, aExp, afrac} = a;