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Seventeen Square Root Tests

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This commit is contained in:
cturek 2022-07-07 22:48:46 +00:00
parent 96a75d7749
commit b41a6f069b
4 changed files with 60 additions and 40 deletions
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5
pipelined/srt/Makefile
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@ -1,7 +1,8 @@
all: exptestgen testgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2
all: exptestgen testgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2 sqrttestgen
sqrttestgen: sqrttestgen.c
gcc sqrttestgen.c -o sqrttestgen -lm
./sqrttestgen
testgen: testgen.c
gcc testgen.c -o testgen -lm
@ -28,5 +29,5 @@ inttestgen: inttestgen.c
./inttestgen
clean:
rm -f testgen exptestgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2
rm -f testgen exptestgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2 sqrttestgen

BIN
pipelined/srt/sqrttestgen
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39
pipelined/srt/sqrttestgen.c
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@ -19,7 +19,7 @@
/* Prototypes */
void output(FILE *fptr, double a, double r);
void output(FILE *fptr, int aExp, double aFrac, int rExp, double rFrac);
void printhex(FILE *fptr, double x);
double random_input(void);
@ -28,12 +28,16 @@ double random_input(void);
void main(void)
{
FILE *fptr;
double a, b, r;
double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
double aFrac, rFrac;
int aExp, rExp;
double mans[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
1.75, 1.875, 1.99999,
1.1, 1.2, 1.01, 1.001, 1.0001,
1/1.1, 1/1.5, 1/1.25, 1/1.125};
int i, j;
double exps[ENTRIES] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15, 16};
int i;
int bias = 1023;
if ((fptr = fopen("sqrttestvectors","w")) == NULL) {
fprintf(stderr, "Couldn't write sqrttestvectors file\n");
@ -41,28 +45,31 @@ void main(void)
}
for (i=0; i<ENTRIES; i++) {
a = list[i];
r = sqrt(a);
output(fptr, a, r);
aFrac = mans[i];
aExp = exps[i] + bias;
rFrac = sqrt(aFrac * pow(2, aExp - bias));
rExp = (int) (log(rFrac)/log(2) + bias);
output(fptr, aExp, aFrac, rExp, rFrac);
}
for (i = 0; i< RANDOM_VECS; i++) {
a = random_input();
r = sqrt(a);
output(fptr, a, r);
}
// for (i = 0; i< RANDOM_VECS; i++) {
// a = random_input();
// r = sqrt(a);
// output(fptr, a, r);
// }
fclose(fptr);
}
/* Functions */
void output(FILE *fptr, double a, double r)
void output(FILE *fptr, int aExp, double aFrac, int rExp, double rFrac)
{
printf("sqrt(%lf) = %lf\n", a, r);
printhex(fptr, a);
fprintf(fptr, "%03x", aExp);
printhex(fptr, aFrac);
fprintf(fptr, "_");
printhex(fptr, r);
fprintf(fptr, "%03x", rExp);
printhex(fptr, rFrac);
fprintf(fptr, "\n");

56
pipelined/srt/testbench.sv
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@ -118,12 +118,11 @@ module testbench;
// Apply directed test vectors read from file.
always @(posedge clk)
begin
r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
rInt = Quot;
if (done) begin
if (~Int) begin
always @(posedge clk) begin
r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)];
rInt = Quot;
if (done) begin
if (~Int & ~Sqrt) begin
req <= #5 1;
diffp = correctr[51:0] - r;
diffn = r - correctr[51:0];
@ -139,24 +138,38 @@ module testbench;
$display("%d Tests completed successfully", testnum);
$stop;
end
end else begin
req <= #5 1;
diffp = correctr[63:0] - rInt;
diffn = rInt - correctr[63:0];
if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
begin
errors = errors+1;
$display("result was %h, should be %h %h %h\n", rInt, correctr, diffn, diffp);
$display("failed\n");
$stop;
end
if (afrac === 52'hxxxxxxxxxxxxx)
end else if (~Sqrt) begin
req <= #5 1;
diffp = correctr[63:0] - rInt;
diffn = rInt - correctr[63:0];
if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
begin
$display("%d Tests completed successfully", testnum);
errors = errors+1;
$display("result was %h, should be %h %h %h\n", rInt, correctr, diffn, diffp);
$display("failed\n");
$stop;
end
end
if (afrac === 52'hxxxxxxxxxxxxx)
begin
$display("%d Tests completed successfully", testnum);
$stop;
end
end else begin
req <= #5 1;
diffp = correctr[51:0] - r;
diffn = r - correctr[51:0];
if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
begin
errors = errors + 1;
$display("result was %h, should be %h %h %h\n", rSqrt, correctr, diffn, diffp);
$display("failed\n");
$stop;
end
if (afrac === 52'hxxxxxxxxxxxxx) begin
$display("%d Tests completed successfully", testnum);
$stop; end
end
end
if (req) begin
req <= #5 0;
correctr = nextr;
@ -169,7 +182,6 @@ module testbench;
{bsign, bExp, bfrac} = b;
nextr = Vec[`memr];
end
end
end
endmodule