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https://github.com/openhwgroup/cvw
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Finalized sqrt, ready for debugging
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@ -57,7 +57,7 @@ module srt (
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logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [`NE-1:0] calcExp;
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logic calcSign;
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logic [`DIVLEN+3:0] X, Dpreproc, C;
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logic [`DIVLEN+3:0] X, Dpreproc, C, F, AddIn;
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logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [$clog2(`XLEN+1)-1:0] intExp, dur, calcDur;
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logic intSign;
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@ -87,17 +87,19 @@ module srt (
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// Divisor Selection logic
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assign Db = ~D;
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mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
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fsel2 fsel(qp, qn, )
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// If only implementing division, use divide otfc
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// otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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// otherwise use sotfc
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creg sotfcC(clk, Start, C);
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sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot, F);
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// Adder input selection
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assign AddIn = Sqrt ? F : Dsel;
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// Partial Product Generation
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
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csa #(`DIVLEN+4) csa(WS, WC, AddIn, qp, WSA, WCA);
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// If only implementing division, use divide otfc
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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// otherwise use sotfc
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// creg sotfcC(clk, Start, C);
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// sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot, F);
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expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
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signcalc signcalc(.XSign, .YSign, .calcSign);
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