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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
moved Ss to execute stage
This commit is contained in:
Katherine Parry
parent
c65aa54a1e
commit
e599f82b29
@ -1 +1 @@
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vsim -c -do "do wally-pipelined-batch.do rv32gc wally32d"
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vsim -c -do "do wally-pipelined-batch.do rv32gc wally32periph"
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@ -44,6 +44,7 @@ module fma(
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output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
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output logic As, // the aligned addend's sign (modified Z sign for other opperations)
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output logic Ps, // the product's sign
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output logic Ss, // the sum's sign
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output logic [$clog2(3*`NF+7)-1:0] NCnt // normalization shift count
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);
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@ -81,7 +82,7 @@ module fma(
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// // Addition/LZA
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// ///////////////////////////////////////////////////////////////////////////////
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add add(.Am, .Pm, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm);
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add add(.Am, .Pm, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Ss);
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loa loa(.A(AmInv+{(3*`NF+6)'(0),InvA&~((ZmSticky&~KillProd))}), .P({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .NCnt);
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endmodule
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@ -226,6 +227,7 @@ module add(
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output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
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output logic NegSum, // was the sum negitive
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output logic InvA, // do you invert the aligned addend
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output logic Ss,
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output logic [3*`NF+5:0] Sm // the positive sum
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);
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logic [3*`NF+6:0] PreSum, NegPreSum; // possibly negitive sum
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@ -257,6 +259,11 @@ module add(
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign Ss = NegSum^Ps; //*** move to execute stage
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endmodule
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@ -114,6 +114,7 @@ module fpu (
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logic NegSumE, NegSumM;
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logic ZSgnEffE, ZSgnEffM;
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logic PSgnE, PSgnM;
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logic SsE, SsM;
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logic [$clog2(3*`NF+7)-1:0] FmaNormCntE, FmaNormCntM;
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// Cvt Signals
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@ -255,36 +256,11 @@ module fpu (
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.Xm(XManE), .Ym(YManE), .Zm(ZManE),
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.XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE),
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.FOpCtrl(FOpCtrlE), .Fmt(FmtE),
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.As(ZSgnEffE), .Ps(PSgnE),
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.As(ZSgnEffE), .Ps(PSgnE), .Ss(SsE),
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.Sm(SumE), .Pe(ProdExpE),
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.NegSum(NegSumE), .InvA(InvAE), .NCnt(FmaNormCntE),
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.ZmSticky(AddendStickyE), .KillProd(KillProdE));
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// // fpdivsqrt using Goldschmidt's iteration
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// if(`FLEN == 64) begin
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// flopenrc #(64) reg_input1 (.d({FSrcXE[63:0]}), .q(DivInput1E),
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// .clear(FDivSqrtDoneE), .en(load_preload),
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// .reset(reset), .clk(clk));
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// flopenrc #(64) reg_input2 (.d({FSrcYE[63:0]}), .q(DivInput2E),
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// .clear(FDivSqrtDoneE), .en(load_preload),
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// .reset(reset), .clk(clk));
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// end
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// else if (`FLEN == 32) begin
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// flopenrc #(64) reg_input1 (.d({32'b0, FSrcXE[31:0]}), .q(DivInput1E),
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// .clear(FDivSqrtDoneE), .en(load_preload),
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// .reset(reset), .clk(clk));
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// flopenrc #(64) reg_input2 (.d({32'b0, FSrcYE[31:0]}), .q(DivInput2E),
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// .clear(FDivSqrtDoneE), .en(load_preload),
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// .reset(reset), .clk(clk));
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// end
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// flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE[0], FOpCtrlE[0]}),
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// .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
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// .clear(FDivSqrtDoneE), .en(load_preload),
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// .reset(reset), .clk(clk));
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// fpdiv_pipe fdivsqrt (.op1(DivInput1E[63:0]), .op2(DivInput2E[63:0]), .rm(FrmE[1:0]), .op_type(FOpCtrlQ),
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// .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
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// .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
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// .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
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divsqrt divsqrt(.clk, .reset, .FmtE, .XManE, .YManE, .XExpE, .YExpE,
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(FDivStartE),
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.StallE, .StallM, .DivStickyM, .DivBusy(FDivBusyE), .DivCalcExpM, //***change divbusyE to M signal
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@ -359,9 +335,9 @@ module fpu (
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{FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM});
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flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM);
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flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
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flopenrc #($clog2(3*`NF+7)+6) EMRegFma4(clk, reset, FlushM, ~StallM,
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{AddendStickyE, KillProdE, InvAE, FmaNormCntE, NegSumE, ZSgnEffE, PSgnE},
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{AddendStickyM, KillProdM, InvAM, FmaNormCntM, NegSumM, ZSgnEffM, PSgnM});
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flopenrc #($clog2(3*`NF+7)+7) EMRegFma4(clk, reset, FlushM, ~StallM,
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{AddendStickyE, KillProdE, InvAE, FmaNormCntE, NegSumE, ZSgnEffE, PSgnE, SsE},
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{AddendStickyM, KillProdM, InvAM, FmaNormCntM, NegSumM, ZSgnEffM, PSgnM, SsM});
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flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,
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{CvtCalcExpE, CvtShiftAmtE, CvtResDenormUfE, CvtResSgnE, IntZeroE, CvtLzcInE},
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{CvtCalcExpM, CvtShiftAmtM, CvtResDenormUfM, CvtResSgnM, IntZeroM, CvtLzcInM});
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@ -381,7 +357,7 @@ module fpu (
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assign FpLoadStoreM = FResSelM[1];
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postprocess postprocess(.Xs(XSgnM), .Ys(YSgnM), .Ze(ZExpM), .Xm(XManM), .Ym(YManM), .Zm(ZManM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(ProdExpM), .DivEarlyTermShift(EarlyTermShiftM),
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.FmaZmS(AddendStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QuotM),
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.FmaZmS(AddendStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QuotM), .FmaSs(SsM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SumM), .DivQe(DivCalcExpM), .DivDone(DivDoneM),
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.FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(ZSgnEffM), .FmaPs(PSgnM), .FOpCtrl(FOpCtrlM), .FmaNCnt(FmaNormCntM),
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.CvtCe(CvtCalcExpM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CvtResSgnM), .ToInt(FWriteIntM), .DivS(DivStickyM),
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@ -52,6 +52,7 @@ module postprocess (
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input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter
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input logic FmaNegSum, // was the sum negitive
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input logic FmaInvA, // do you invert Z
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input logic FmaSs,
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input logic [$clog2(3*`NF+7)-1:0] FmaNCnt, // the normalization shift count
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//divide signals
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input logic [`DURLEN-1:0] DivEarlyTermShift,
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@ -197,7 +198,7 @@ module postprocess (
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roundsign roundsign(.FmaPs, .FmaAs, .FmaInvA, .FmaOp, .DivOp, .CvtOp, .FmaNegSum,
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.Xs, .Ys, .CvtCs, .Ms);
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.FmaSs, .Xs, .Ys, .CvtCs, .Ms);
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round round(.OutFmt, .Frm, .S, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe,
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.Ms, .FmaSe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf,
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@ -38,23 +38,15 @@ module roundsign(
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input logic DivOp,
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input logic CvtOp,
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input logic CvtCs,
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input logic FmaSs,
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output logic Ms
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);
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logic FmaResSgnTmp;
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logic Qs;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign FmaResSgnTmp = FmaNegSum^FmaPs; //*** move to execute stage
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// assign FmaResSgnTmp = FmaInvA&(FmaAs)&FmaNegSum | FmaInvA&FmaPs&~FmaNegSum | (FmaAs&FmaPs);
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assign Qs = Xs^Ys;
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// Sign for rounding calulation
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assign Ms = (FmaResSgnTmp&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp);
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assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp);
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endmodule
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@ -94,6 +94,7 @@ module testbenchfp;
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// in-between FMA signals
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logic Mult;
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logic Ss;
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logic [`NE+1:0] Pe;
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logic ZmSticky;
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logic KillProd;
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@ -674,13 +675,13 @@ module testbenchfp;
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fma fma(.Xs(XSgn), .Ys(YSgn), .Zs(ZSgn),
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.Xe(XExp), .Ye(YExp), .Ze(ZExp),
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.Xm(XMan), .Ym(YMan), .Zm(ZMan),
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.XZero, .YZero, .ZZero,
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.XZero, .YZero, .ZZero, .Ss,
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.FOpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .NCnt, .As, .Ps,
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.Pe, .ZmSticky, .KillProd);
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postprocess postprocess(.Xs(XSgn), .Ys(YSgn), .PostProcSel(UnitVal[1:0]),
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.Ze(ZExp), .ZDenorm(ZDenorm), .FOpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
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.Xm(XMan), .Ym(YMan), .Zm(ZMan), .CvtCe(CvtCalcExpE), .DivS(DivSticky),
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.Xm(XMan), .Ym(YMan), .Zm(ZMan), .CvtCe(CvtCalcExpE), .DivS(DivSticky), .FmaSs(Ss),
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.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResDenormUf(CvtResDenormUfE),
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.XZero(XZero), .YZero(YZero), .ZZero(ZZero), .CvtShiftAmt(CvtShiftAmtE),
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.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
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