134 Commits

Author	SHA1	Message	Date
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	bea8ac6d59	WALLY-LRSC atomic test passing	2021-03-09 09:28:25 -05:00
Ross Thompson	d6bc34121f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-05 15:27:22 -06:00
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	ca2a65770c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 15:46:51 -05:00
Thomas Fleming	85dcbee86b	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
Noah Boorstin	0af002eb2f	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
Teo Ene	2723b21988	Linux CoreMark and baremetal CoreMark split into two separate tests/configs	2021-03-04 07:44:33 -06:00
Teo Ene	80f6d6c944	Linux CoreMark is operational	2021-03-04 05:58:18 -06:00
Teo Ene	0c009fb1e6	In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches	2021-03-04 01:27:05 -06:00
Noah Boorstin	f11b3108d8	busybear: fix bootram range	2021-03-01 17:45:21 +00:00
Noah Boorstin	2769b147cb	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
Noah Boorstin	969c094489	busybear: remove gpio, start adding 2nd ram	2021-02-28 06:02:40 +00:00
Teo Ene	b9701293a0	Changed TIMBASE in coremark config file	2021-02-25 11:03:41 -06:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
Teo Ene	cfd45a46c3	Added provisional coremark files from work with Elizabeth	2021-02-24 20:07:07 -06:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
Noah Boorstin	cca60ed06d	update busybear testbench to conform to new structure ... aaaaaaaaaaaaaaaaaahhhh so many changes also the testbench now uses another internal signal, which I don't like, but I can't think of a better option rn	2021-01-30 19:19:00 +00:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9530039e3d	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
Teo Ene	f0bbd71874	Added AHBW to rv32ic config file as well	2021-01-29 12:29:08 -06:00
Noah Boorstin	7183910c84	update busybear testbench to conform to new structure	2021-01-29 17:46:50 +00:00
David Harris	4687d6998a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-01-29 01:07:22 -05:00
David Harris	e4e95bf941	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
Noah Boorstin	0fa7cffb11	busybear: lie about MISA to match OVP's MISA	2021-01-29 00:58:56 -05:00
David Harris	4318629b32	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
Noah Boorstin	91dcffa26f	Update busybear tests to conform to new directory structure	2021-01-25 20:37:18 -05:00
David Harris	b7988e536f	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00