David Harris
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a5a89e58a8
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Fixed unpacking bug; regression runs again
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2022-01-06 18:22:30 +00:00 |
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David Harris
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eff9cec415
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-06 18:10:32 +00:00 |
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David Harris
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aca26de498
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FPU debug and configurable logic cleanup
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2022-01-06 18:10:25 +00:00 |
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Ross Thompson
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6edd4c5759
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-06 11:56:23 -06:00 |
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Ross Thompson
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c19b910f6e
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Updated fpga ILA constraints to match the new changes to the rtl.
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2022-01-06 11:56:09 -06:00 |
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Ross Thompson
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8e10e15c64
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Fixed bug in synthesis script.
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2022-01-05 23:07:36 -06:00 |
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Ross Thompson
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f604a0d79e
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cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
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2022-01-05 22:56:18 -06:00 |
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Ross Thompson
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a4afc1bc54
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More name cleanup in cache.
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2022-01-05 22:37:53 -06:00 |
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Ross Thompson
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e74e8c2e86
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Changed names of address in caches.
Removed old cache files.
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2022-01-05 22:19:36 -06:00 |
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Ross Thompson
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1ab3a17ff7
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Updates to support fpga.
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2022-01-05 18:07:23 -06:00 |
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Ross Thompson
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9ea34e390a
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Fixed xilinx synth error with $error in extend.sv
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2022-01-05 17:48:08 -06:00 |
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Kip Macsai-Goren
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c949764a44
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fixed 32 vs 64 bit copying error
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2022-01-05 23:14:12 +00:00 |
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Ross Thompson
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de32930e63
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-05 16:57:29 -06:00 |
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Ross Thompson
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da585b30f9
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Slower but correct implementation of flush.
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2022-01-05 16:57:22 -06:00 |
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David Harris
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fed44cf9cf
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Reinstated many arch f/d tests that had failed because of memfile issues
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2022-01-05 22:44:10 +00:00 |
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David Harris
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8305eb80ff
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Restored many of the arch32f and arch64d that had been failing because of memfile issues
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2022-01-05 22:23:46 +00:00 |
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David Harris
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27771f1756
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 22:10:50 +00:00 |
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Kip Macsai-Goren
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5754e16390
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 22:10:37 +00:00 |
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David Harris
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90dd961ea5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 22:10:33 +00:00 |
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David Harris
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07932ad0aa
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Replaced exe2memfile with SiFive elf2hex
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2022-01-05 22:10:26 +00:00 |
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Kip Macsai-Goren
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bd977efc7b
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updated pma tests for simpler test lib
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2022-01-05 22:10:12 +00:00 |
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kipmacsaigoren
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900c1bfc9e
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Added the config file to the outputs of synth
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2022-01-05 16:08:31 -06:00 |
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Kip Macsai-Goren
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8a8f903342
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updated tests to make correctly with output verification
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2022-01-05 21:43:15 +00:00 |
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Kip Macsai-Goren
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706c95a383
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allowed option for tests to make without spike simulation. added postverify back in for outputs
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2022-01-05 21:17:54 +00:00 |
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Kip Macsai-Goren
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1db58744b0
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updated pma tests to match simpler test library. They don't pass regression yet
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2022-01-05 21:13:40 +00:00 |
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Kip Macsai-Goren
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cc47b419be
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 20:17:52 +00:00 |
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Ross Thompson
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0310df96a4
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Changes to wave file.
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2022-01-05 14:16:59 -06:00 |
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Ross Thompson
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7086a0ed08
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-05 14:15:27 -06:00 |
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Ross Thompson
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cc51a27a34
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Fixed bug with flush dirty not cleared in the correct cache line.
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2022-01-05 14:14:01 -06:00 |
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davidharrishmc
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d0d9f73794
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Update README.md
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2022-01-05 11:29:54 -08:00 |
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Kip Macsai-Goren
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b53ab27b26
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 18:38:29 +00:00 |
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James E. Stine
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edbaff4ea3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 10:44:28 -06:00 |
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James E. Stine
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962e7dc782
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Add script to generate memfile using elf2hex
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2022-01-05 10:44:01 -06:00 |
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David Harris
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d17a305538
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Finished removing generate statements
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2022-01-05 16:41:17 +00:00 |
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David Harris
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6d4714651c
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Removed more generate statements
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2022-01-05 16:25:08 +00:00 |
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David Harris
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da5ead23bf
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Removed more generate statements
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2022-01-05 16:01:03 +00:00 |
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David Harris
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d66f7c841b
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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Ross Thompson
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98be8201b2
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Renamed most signals inside cache.sv so they are agnostic to i or d.
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2022-01-04 23:52:42 -06:00 |
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Ross Thompson
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fffaf654e6
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the i and d caches now share common verilog.
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2022-01-04 23:40:37 -06:00 |
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Ross Thompson
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13dbf3cc0f
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parameterized the caches with the goal of using common rtl for both i and d caches.
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2022-01-04 22:40:51 -06:00 |
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Ross Thompson
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888a60d8d6
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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Ross Thompson
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cb301a78ad
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Fixed bug where last line of dcache was not written back to memory on dcache flush.
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2022-01-04 21:55:48 -06:00 |
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Ross Thompson
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101a8bdb5b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-04 18:41:52 -06:00 |
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Ross Thompson
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ecc7bf5237
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Fixed dcache flush.
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2022-01-04 18:40:58 -06:00 |
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David Harris
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9ddc6db0a6
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Removed imperas mmu tests; using wallypriv instead
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2022-01-04 23:14:53 +00:00 |
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Kip Macsai-Goren
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04bcf5ef38
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cleaned up Imperas tests to pass make
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2022-01-04 21:32:21 +00:00 |
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Kip Macsai-Goren
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c65fc4d5e6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-04 21:30:51 +00:00 |
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Kip Macsai-Goren
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46b0cb810d
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fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.
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2022-01-04 21:30:38 +00:00 |
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David Harris
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0a7ec3e58d
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Fixed bad address for F/fmsub_b18-01
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2022-01-04 21:04:06 +00:00 |
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Kip Macsai-Goren
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5218533ddc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-04 20:58:08 +00:00 |
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