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Configurable RISC-V Processor
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David Harris 8305eb80ff Restored many of the arch32f and arch64d that had been failing because of memfile issues
2022-01-05 22:23:46 +00:00
addins Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
benchmarks/riscv-coremark Added file showing how to compile riscv toolchain for different extension combinations. 2021-12-19 20:31:55 -06:00
bin Replaced exe2memfile with SiFive elf2hex 2022-01-05 22:10:26 +00:00
examples Added performance counting to sumtest and added imperas32/64periph to testbench. 2021-12-29 00:28:51 +00:00
fpga Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
pipelined Restored many of the arch32f and arch64d that had been failing because of memfile issues 2022-01-05 22:23:46 +00:00
tests updated pma tests for simpler test lib 2022-01-05 22:10:12 +00:00
.gitattributes Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
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README.md Update README.md 2022-01-05 11:29:54 -08:00
setup.sh Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wallyVirtIO.patch added wallyVirtIO.patch from Ross 2021-12-22 07:04:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.