77 Commits

Author	SHA1	Message	Date
David Harris	b4dd7b21e6	generic cleanup	2023-01-14 19:02:38 -08:00
David Harris	fa61c9c4a5	generic cleanup	2023-01-14 18:56:46 -08:00
David Harris	e67f125201	Header comments	2023-01-12 04:35:44 -08:00
Katherine Parry	4079f76a78	cleaned up all FPU files except for division	2023-01-11 22:02:30 -06:00
David Harris	7d93659f6b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
Ross Thompson	34f8f2c47a	Added more missing files.	2023-01-06 00:12:08 -06:00
Ross Thompson	5d844801d2	Fixed problems with changes to ram2p.	2022-12-29 17:13:48 -06:00
Ross Thompson	5d91434b32	signal name changes in ram2p.	2022-12-27 15:07:01 -06:00
David Harris	8f0ef29349	Memory cleanup	2022-12-20 11:22:26 -08:00
David Harris	c26c3b76ea	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
David Harris	1ec62606f9	sram1p1rw cleanup	2022-12-20 02:57:51 -08:00
David Harris	0883736c88	Remoed unused bram modules	2022-12-20 02:40:45 -08:00
David Harris	9ad5552e89	Renamed SRAM2P1R1W to lower case	2022-12-20 02:09:55 -08:00
David Harris	b575f6242e	Renamed SRAM2P1R1W to lower case	2022-12-20 02:09:36 -08:00
Ross Thompson	de538d1c2f	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
Ross Thompson	00218d559f	Missing a file. Last commit will fail.	2022-11-17 17:45:41 -06:00
Ross Thompson	13e6f7d80b	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
David Harris	713df785d1	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
Ross Thompson	2eaf3af6c7	Removed the write first sram model.	2022-09-22 16:12:08 -05:00
Ross Thompson	b48d6b5e1f	Solved the sram write first / read first issue. Works correctly with read first now.	2022-09-22 14:16:26 -05:00
Ross Thompson	3fb0a13fe2	Moved other SRAMs to generic/mem.	2022-09-21 12:36:03 -05:00
Ross Thompson	66c45949b5	Renamed brom1p1r to rom1p1r. ... removed used file bram2p1r1w.sv.	2022-09-21 12:31:20 -05:00
Ross Thompson	ac864a6ca3	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
Ross Thompson	426ec6222b	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
David Harris	2d5e7827df	Factored out aplusbeq0 unit	2022-09-07 11:36:35 -07:00
Ross Thompson	7ad7cea25b	James found a bug in synchronizer. Was not actually back to back flip flops.	2022-09-06 15:06:54 -05:00
Ross Thompson	5d2b299182	Fixed brom1p1r.sv to have fpga preload.	2022-09-02 15:49:50 -05:00
Ross Thompson	4d60d9a840	Fixed up FPGA constraints. ... Added back in the fpga boot rom preload.	2022-09-02 13:54:35 -05:00
David Harris	19fe6d106c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:52:49 -07:00
Ross Thompson	ad485fe591	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:03:34 -05:00
Ross Thompson	701324eeb8	Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.	2022-08-25 09:03:29 -05:00
David Harris	3500286803	Cleanup typos	2022-08-25 04:32:19 -07:00
David Harris	f7209627c2	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
David Harris	a131e1f17a	Added ROM module and moved memories into generic/mem	2022-08-24 17:03:22 -07:00
Ross Thompson	d23b309e0d	Fixed lint errors with bram wrapper.	2022-08-24 13:19:23 -05:00
David Harris	bcb52acfba	bram synthesis test	2022-08-23 19:34:45 -07:00
Ross Thompson	3b07584403	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00
David Harris	bdfc49f847	moved CSA to generic	2022-08-22 08:41:23 +00:00
Katherine Parry	3c1bea1104	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
Katherine Parry	75a8cea4e4	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
Madeleine Masser-Frye	52562c9190	new priority onehot module for better area/time	2022-07-06 00:08:59 +00:00
Katherine Parry	2fc795ca70	added missing files	2022-07-03 21:40:47 -07:00
slmnemo	bca8fe1694	Removed big64.txt reference, fixing a warning	2022-06-23 14:39:53 -07:00
David Harris	cc06fa1c55	Cleaned bram interface	2022-06-08 01:39:44 +00:00
David Harris	f81719337e	Added ahbapbbridge and cleaning RAM	2022-06-08 01:31:34 +00:00
Katherine Parry	74b549ddc8	paramerterized some small fma units	2022-06-01 23:34:29 +00:00
Katherine Parry	559c0c278e	added unpackinput.sv	2022-05-31 16:18:50 +00:00
Katherine Parry	3c63db9554	some optimizations in unpacker	2022-05-27 11:36:04 -07:00