Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-01 17:34:27 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,553 Commits 4 Branches 2 Tags 53 MiB
a4c7d1d936
Commit Graph

813 Commits

Author SHA1 Message Date
DTowersM
4fbce9fc45 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-01 21:00:51 +00:00
DTowersM
d3c8ee7154 added support for embench post processing to testbench.sv 2022-06-01 21:00:44 +00:00
Katherine Parry
707067548f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
108f32e9df Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
cturek
e3a0ee333f Fixed typos 2022-06-01 00:07:36 +00:00
slmnemo
56121b3587 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
2b80788235 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
c24f88c2e9 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
efe4b3e8fe Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
99da6537cc Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
79df271a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
31815422d2 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
DTowersM
f7491e8445 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 20:13:41 +00:00
DTowersM
2088c0cd7c added testbench.sv support for embench tests, test output still WIP 2022-05-31 20:13:32 +00:00
DTowersM
abb6ba97cf removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM 2022-05-31 20:10:56 +00:00
DTowersM
ea07588999 added embench tests to tests.vh 2022-05-31 20:08:04 +00:00
Katherine Parry
cd7fe9af61 reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
559c0c278e added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
2935188035 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
d1ef3b8981 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
835a4e4606 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
3b9ae58f59 Reverted commit 9b55e9da38 2022-05-28 04:00:01 -07:00
slmnemo
2f3689063a Revert Commit 61ebf68939 2022-05-28 03:35:17 -07:00
slmnemo
9b55e9da38 Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name 2022-05-28 03:16:55 -07:00
slmnemo
61ebf68939 Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do 2022-05-28 03:14:49 -07:00
slmnemo
f426850bc7 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
80315fedff fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4335895b21 Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
822866fd0a removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
d5c249bf71 unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
3c63db9554 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
b288f812ab moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
efb972c6d3 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bddc32ed21 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
efce3e4953 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
cturek
f7a3855af1 fixed sizing issues in expcalc 2022-05-26 22:35:17 +00:00
cturek
a025014650 Implemented on-the-fly conversion for unsigned numbers 2022-05-26 22:20:43 +00:00
Katherine Parry
b13c3d5385 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 20:48:30 +00:00
Katherine Parry
550c4d380c fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
ae460eccd4 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
DTowersM
ea882e7271 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 19:05:21 +00:00
DTowersM
a983791d64 fixed indent spacing (cosmetic change) 2022-05-26 19:04:21 +00:00
cturek
0f1da722bf Set up the divider for on-the-fly conversion 2022-05-26 16:45:28 +00:00
slmnemo
80965f953c added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
1d3752b0b3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:41:04 -07:00
slmnemo
466fb71add added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction 2022-05-25 17:40:57 -07:00
slmnemo
87cfd62e19 Added line to testbench to prevent annoying burst sizes 2022-05-25 17:29:45 -07:00
slmnemo
95d64fe4ae idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
DTowersM
41f6233a70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 00:12:46 +00:00
slmnemo
3efe43af60 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:11:03 -07:00
slmnemo
5a9e3a852a see commit 9042cc3c 2022-05-25 17:10:59 -07:00
Katherine Parry
f4b9ade942 added fcvt.sv 2022-05-26 00:10:51 +00:00
DTowersM
aa574d545c Merge branch 'embench' into main 
embench contained the working makefiles for embench and is being merged into main as it working and done
 2022-05-26 00:10:50 +00:00
DTowersM
5e87506772 working makefile for embench and removed testbench-f64 2022-05-26 00:08:18 +00:00
slmnemo
17dff315f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:03:26 -07:00
slmnemo
d43d340e31 added logic to prevent cache line length from exceeding the max size of a burst. 2022-05-25 17:03:15 -07:00
cturek
366cd5f1d5 Renamed variables for readability 2022-05-26 00:01:51 +00:00
cturek
650779318d Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
c8892f2847 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
7d1448d2ad added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
slmnemo
cd9f0cd6bd fixed a comment spelling typo 2022-05-23 19:24:28 -07:00
Katherine Parry
18bdaf0179 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-23 23:11:41 +00:00
Katherine Parry
37e74648a9 added exponents to srt divider 2022-05-23 23:07:27 +00:00
David Harris
2d175e2a37 Checked in qst2.c from James 2022-05-23 20:26:05 +00:00
Ross Thompson
1dde9db2ce Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
13f7f48776 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
99aa110615 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
378523087f added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
ff8e158ec4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
848abf29b5 Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
0bcae85792 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
fcaf032a0d ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
slmnemo
a5d5bd272b changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
Katherine Parry
6bc31f2e78 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
af675bbefb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 18:31:56 -07:00
slmnemo
4a2538455d added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
slmnemo
3b4286ec33 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
6c237e43d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
a5490c7096 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
05d14bdb3c Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
0982417054 Fixed buildroot by adding a second . 2022-05-19 17:49:32 -07:00
slmnemo
7d2bfb6db8 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
bc4804d90a fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
b0881495a9 Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
b255f61521 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
710905b239 updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
cc0ab94ebc Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
af14c8a064 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
mmasserfrye
1442afe4e2 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
1888a9a665 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-18 16:10:36 +00:00
mmasserfrye
0265d1988e adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
slmnemo
7cd673fa6e simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
ebeebf3bfc Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." 
This reverts commit 910475ea56.

gottem
 2022-05-17 17:26:33 -07:00
slmnemo
910475ea56 same as last breaking commit, testing if the bisect works to output a breaking commit. 2022-05-17 17:22:09 -07:00
slmnemo
36ea0f9126 Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." 
This reverts commit 0dea11fc73.

fixed it
 2022-05-17 17:05:11 -07:00
slmnemo
0dea11fc73 broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. 2022-05-17 17:03:16 -07:00
slmnemo
73d19b0956 Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" 
This reverts commit 83e4ab711c.

unbroke wally
 2022-05-17 16:57:29 -07:00