Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,011 Commits 5 Branches 2 Tags 53 MiB
a12016e69b
Commit Graph

3011 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Kip Macsai-Goren
6ed96761b6 Merge small mmu changes into main 2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
be99c18002 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
41ceb20296 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
e044f72e59 remove redundant decodes, fixed mmu logic ins/outs 2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
146ed95bdb got rid of some underscores in filenames, modules 2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
55d50f5607 began updating cam line to reduce muxes, confusion 2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
1377680270 regression working partially done page mask 2021-06-07 17:02:31 -04:00
David Harris
4740ef97d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-07 16:14:13 -04:00
David Harris
c3d21967f8 Simplified superpage matching 2021-06-07 16:11:28 -04:00
Katherine Parry
b55798f09b lint is clean 2021-06-07 14:22:54 -04:00
bbracker
3e11da2aa2 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
b37bcc8e38 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
d69501c4fa Cleaned up some unused signals 2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
b99b5f8e0e moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
4a00fbaf04 Merge branch 'mmu' into main 
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
 2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
318a547531 added shared constants file list of includes 2021-06-04 17:05:47 -04:00
Kip Macsai-Goren
7e41b17e65 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
Ross Thompson
6f58c66be8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
e200b4b5a4 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2 Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Ross Thompson
fdc7c673dd Cleaned up the I-Cache memory. 2021-06-04 13:36:06 -05:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
2c16591396 Reorganized the icache names. 2021-06-04 12:53:42 -05:00
Ross Thompson
147be536f1 Relocated the icache to the cache directoy. 2021-06-04 12:23:46 -05:00
Ross Thompson
b739853784 Added special tests for checking the accuracy of global and gshare branch 
predictors.
 2021-06-04 11:01:54 -05:00
David Harris
b836679ae1 Started MMU 2021-06-04 11:59:14 -04:00
Ross Thompson
976b612992 updated isa extensions for simple branch predictor test. 2021-06-04 10:41:32 -05:00
David Harris
99d661cee9 Fixed RV32 MMU constants 2021-06-04 09:15:42 -04:00
David Harris
a61411995a moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
1b2822e078 added support for sv48 and some docs on how to use these files 2021-06-03 14:32:12 -04:00
Kip Macsai-Goren
a84dd6dfc5 added tests for SV48 and translation off with vmem 2021-06-03 14:28:52 -04:00
bbracker
d8913e5547 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-03 10:03:26 -04:00
bbracker
8338b3bd34 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
987460c49a reached a good stopping point on buildroot progress; parse_qemu.py has been rewritten for readability and QEMU MMU failure workaround 2021-06-03 10:00:16 -04:00
Ross Thompson
db2a38c300 Fixed a few lint errors, 
clock gater was wrong,
missing signal definitions in branch predictor.
 2021-06-02 09:33:24 -05:00
bbracker
4f03ecb6ec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-02 10:03:23 -04:00
bbracker
28abd28b1f fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
f7deda0514 implemented Sv48. 2021-06-01 17:50:37 -04:00
Kip Macsai-Goren
06cf3a8403 Edited and added constants to support SV48 2021-06-01 17:49:45 -04:00
James E. Stine
7f5e5287b0 delete div.bak 2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877 The clock gater was not implemented correctly. Now it is level sensitive to a low clock. 2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3 Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00