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Configurable RISC-V Processor
920 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
db2a38c300
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Ross Thompson db2a38c300 Fixed a few lint errors, 
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
riscv-coremark commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Now have global history working correctly. 2021-06-01 10:57:43 -05:00
wally-pipelined Fixed a few lint errors, 2021-06-02 09:33:24 -05:00
.gitignore script for running make and logging output 2021-05-17 22:12:18 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor