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Configurable RISC-V Processor
953 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Kip Macsai-Goren 55d50f5607 began updating cam line to reduce muxes, confusion
2021-06-07 17:03:31 -04:00
riscv-coremark commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
sky130
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined began updating cam line to reduce muxes, confusion 2021-06-07 17:03:31 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore script for running make and logging output 2021-05-17 22:12:18 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor