Jordan Carlin
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4929581576
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Cleanup
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2024-08-30 11:57:31 -07:00 |
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Rose Thompson
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f1d9e18dee
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Modified fpga config to support two fpga boards with different amount of memory.
Modified vcu108 constraints to better constrain the spi clock and in/out.
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2024-08-29 16:12:58 -07:00 |
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Jordan Carlin
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80750f2308
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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
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2024-08-29 15:55:54 -07:00 |
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David Harris
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a9d904caf1
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-08-29 15:43:04 -07:00 |
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David Harris
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ffd4d71fe5
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Merge pull request #938 from ross144/main
Fixed basic support for open source riscvISACOV
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2024-08-29 15:42:40 -07:00 |
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Rose Thompson
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587a65aa75
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-29 15:30:45 -07:00 |
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Rose Thompson
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e07f303353
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Have basic rv32gc functional coverage running with open source riscvISACOV.
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2024-08-29 15:29:04 -07:00 |
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David Harris
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6157023d16
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-08-29 15:07:18 -07:00 |
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David Harris
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636a8cbbd6
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Merge pull request #937 from ross144/main
Fixed questa and ImperasDV library issue
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2024-08-29 15:00:18 -07:00 |
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Rose Thompson
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dc9a77e45a
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Updated riscvISACOV submodule to https instead of ssh.
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2024-08-29 14:54:47 -07:00 |
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Rose Thompson
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a1c6bc854e
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Fixed a subtle questa sim bug with imperasDV. On some linux systems
vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV
libraries are 64-bit. vsim must run in 64-bit mode.
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2024-08-29 14:00:52 -07:00 |
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David Harris
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0e9e7d0a49
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Fixed wallyTracer floating-point register FLEN
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2024-08-29 11:11:19 -07:00 |
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Rose Thompson
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0ce4d1b452
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-29 10:50:27 -07:00 |
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Rose Thompson
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6ad2c2e7a6
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Merge pull request #935 from davidharrishmc/dev
Added lockstep support for RV32. Not all wally privileged tests pass…
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2024-08-29 10:45:17 -07:00 |
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David Harris
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26f3c2a607
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Added lockstep support for RV32. Not all wally privileged tests pass yet
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2024-08-29 10:44:37 -07:00 |
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David Harris
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ca4dcfdaa9
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Merge pull request #934 from JacobPease/main
Custom test spitest fix
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2024-08-28 02:13:06 -07:00 |
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Jacob Pease
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c4d909c412
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-28 04:10:38 -05:00 |
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Jacob Pease
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3b91977227
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Added start.s to spitest directory.
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2024-08-28 04:10:24 -05:00 |
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Rose Thompson
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cb05697698
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Added basic SPI signals to waveform.
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2024-08-27 15:51:19 -07:00 |
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Rose Thompson
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7e16ddd859
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Improved fpga synth script.
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2024-08-27 15:50:05 -07:00 |
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Rose Thompson
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e5d3462a90
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Converted wall.tcl to entirely project mode.
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2024-08-27 14:15:58 -07:00 |
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Rose Thompson
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0ce289c937
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Merge pull request #933 from JacobPease/main
Committing the custom test spitest.
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2024-08-27 12:43:19 -07:00 |
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Jacob Pease
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44ece7cb96
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Added CVW header to spitest files.
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2024-08-27 14:28:49 -05:00 |
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Jacob Pease
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b7a74307c5
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Committing the custom test spitest.
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2024-08-27 14:19:56 -05:00 |
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Rose Thompson
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2dd897e7e1
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Merge pull request #932 from davidharrishmc/dev
Added temporary --fcov2 option to start adopting open-source riscvISACOV
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2024-08-27 08:47:59 -07:00 |
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David Harris
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9df38e14b2
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Added temporary --fcov2 option to start adopting open-source riscvISACOV
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2024-08-27 08:40:44 -07:00 |
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Rose Thompson
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f20a1564fa
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Added SPI debugger.
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2024-08-26 17:22:13 -07:00 |
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Rose Thompson
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f31eb62c1b
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Merge pull request #929 from JacobPease/main
Bootloader Speed Improvements
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2024-08-26 09:10:42 -07:00 |
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Jordan Carlin
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0c4993e1db
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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
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2024-08-25 14:57:22 -07:00 |
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Jordan Carlin
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99da7e7b21
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Merge pull request #931 from davidharrishmc/dev
Fixed imperas configuration and updated files for new Imperas/Synopsy…
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2024-08-25 14:55:42 -07:00 |
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David Harris
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30694f4ed0
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Fixed imperas configuration and updated files for new Imperas/Synopsys licenses
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2024-08-25 14:46:22 -07:00 |
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Jordan Carlin
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f0c5d6e4e7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
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2024-08-25 12:14:25 -07:00 |
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Jacob Pease
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d649473ec8
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-24 21:57:44 -05:00 |
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Jacob Pease
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ad6734eb6d
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Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full.
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2024-08-24 21:36:29 -05:00 |
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David Harris
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86aaf43306
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Merge pull request #928 from ross144/main
Update FPGA constraints to restore support for VCU108 and increase speed to 50MHz
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2024-08-24 18:45:55 -07:00 |
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Rose Thompson
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ea181a2ba3
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-23 17:37:14 -07:00 |
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Rose Thompson
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ee1e09a6a2
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VCU108 now boot linux at 50MHz!
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2024-08-23 17:18:47 -07:00 |
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Rose Thompson
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14083bc642
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VCU108 is not synthesizing at 50MHz. Still running into a few problems
with the new SPI sd card device.
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2024-08-23 16:17:15 -07:00 |
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Rose Thompson
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842aea157c
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Updated vc108 constraints for spi based sd card and setting 50 Mhz.
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2024-08-23 15:59:11 -07:00 |
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Rose Thompson
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167878aee4
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Commet out debug code in fpga synth script.
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2024-08-23 14:46:01 -07:00 |
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Rose Thompson
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b471913d9f
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On the way to making vcu108 work again.
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2024-08-23 14:45:22 -07:00 |
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Rose Thompson
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4d56b3ca96
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Maybe improvements to fpga synthesis.
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2024-08-23 13:00:22 -07:00 |
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David Harris
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aba4caa108
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Merge pull request #927 from 10x-Engineers/rvvi_setup
Removing warnings from questa simulation
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2024-08-23 06:34:35 -07:00 |
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Huda-10xe
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da2c9a5dc5
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Removing warnings from questa simulation
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2024-08-23 12:37:42 +05:00 |
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Rose Thompson
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fc80bf1251
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More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
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Rose Thompson
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8d40a0a092
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Changed names of fpga IP modules to match textbook. Updated boot.h to
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
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2024-08-22 13:56:50 -07:00 |
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David Harris
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b4bcd7b0b1
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Merge pull request #926 from ross144/main
Fix my name on multiple files and other minor changes
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2024-08-22 03:23:17 -07:00 |
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Rose Thompson
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418bc6b23c
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-21 16:24:10 -07:00 |
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Rose Thompson
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1f57fd6343
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Fixed bug in Makefile.
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2024-08-21 16:04:21 -07:00 |
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Rose Thompson
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249db9cf45
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Merge pull request #925 from JacobPease/main
Update PREADY signal to not stall during transmission on reads to read only registers.
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2024-08-21 12:44:57 -07:00 |
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