17 Commits

Author	SHA1	Message	Date
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	6966554ee8	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	0340c0fd44	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
Kip Macsai-Goren	ad106e7130	made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes	2022-03-29 02:26:42 +00:00
Ross Thompson	7099259ff7	I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.	2022-03-25 13:10:31 -05:00
bbracker	9f60256f22	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	6ab14d7302	Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.	2022-03-22 22:04:06 -05:00
David Harris	d8170e9dd3	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00