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83 lines
3.9 KiB
Systemverilog
83 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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// csri.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Interrupt Control & Status Registers (IP, EI)
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// See RISC-V Privileged Mode Specification 20190608 & 20210108 draft
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module csri #(parameter
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MIE = 12'h304,
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MIP = 12'h344,
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SIE = 12'h104,
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SIP = 12'h144
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) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [11:0] CSRAdrM,
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(* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt,
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output logic [11:0] MIP_REGW, MIE_REGW,
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(* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
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);
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logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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// Interrupt Write Enables
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assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM;
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assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM;
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assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM;
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assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM;
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// Interrupt Pending and Enable Registers
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// MEIP, MTIP, MSIP are read-only
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// SEIP, STIP, SSIP is writable in MIP if S mode exists
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// SSIP is writable in SIP if S mode exists
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if (`S_SUPPORTED) begin:mask
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assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
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assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3)
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assign MIE_WRITE_MASK = 12'hAAA;
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end else begin:mask
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assign MIP_WRITE_MASK = 12'h000;
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assign SIP_WRITE_MASK = 12'h000;
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assign MIE_WRITE_MASK = 12'h888;
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end
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always @(posedge clk)
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if (reset) MIP_REGW_writeable <= 12'b0;
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else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK);
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else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK);
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always @(posedge clk)
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if (reset) MIE_REGW <= 12'b0;
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else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
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else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields
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assign MIP_REGW = {MExtInt,1'b0,SExtInt|MIP_REGW_writeable[9],1'b0,MTimerInt,1'b0,MIP_REGW_writeable[5],1'b0,MSwInt,1'b0,MIP_REGW_writeable[1],1'b0};
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endmodule
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