Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
3bed733301
Fixed fpga to work with the updated regression changes.
2024-04-22 10:42:01 -05:00
Rose Thompson
cc7f433ce0
Update the fpga scripts to use the new derivative configs.
2024-01-31 13:19:28 -06:00
Rose Thompson
34631c54d3
Get's the fpga building again after the git history rewrite.
2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b
Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12
Modified FPGA Makefile to override with relative path. FPGA boots now.
2023-11-30 17:51:15 -06:00
Rose Thompson
d4bc9da085
Fixed another bug in the updated script changes.
2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0
Fixed bugs in the updated fpga synthe script.
2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 17:48:28 -06:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Jacob Pease
9d33e08dbb
Removed non-existent SDC dependency from VCU targets in FPGA Makefile.
2023-07-27 15:01:20 -05:00
Ross Thompson
ab6ef5bb58
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
6907f0ccc1
FPGA makefile update.
2023-04-25 16:24:26 -05:00
Ross Thompson
f22e6d0e48
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 11:08:35 -05:00
Ross Thompson
5591b447d6
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
777edb0fcd
Progress on arty a7 board.
2023-04-13 17:57:12 -05:00
Ross Thompson
e490ab09cf
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
9d9c2b170d
Finally building ddr3 xilinx ip from script.
2023-04-10 14:36:33 -05:00
Jacob Pease
45b264fa59
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Jacob Pease
07e279b5b5
Modified makefile. Added axi protocol converter IP.
2023-01-23 19:30:29 -06:00
Jacob Pease
9b612fbf6c
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-01-23 12:41:02 -06:00
Ross Thompson
0ed9811e31
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
9c83b2dff5
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
25bd2e4670
Removed mark_debug vivado directive from source code.
...
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
5b740fbf60
Removed SDC from repo due to copy right issue.
...
Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Jacob Pease
e5d4277406
Connected the axi_sdc_controller with an axi crossbar.
...
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
2023-01-13 13:56:01 -06:00
Ross Thompson
15042fc856
Updated fpga constraints.
2022-12-21 14:50:01 -06:00
Ross Thompson
5c49cc4dd0
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Ross Thompson
9ba487c323
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
bb79f70a63
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
35dd1b5c9f
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 10:05:13 -06:00
Ross Thompson
7f52d86980
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
