mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 05:24:49 +00:00
70 lines
1.7 KiB
Makefile
70 lines
1.7 KiB
Makefile
dst := IP
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# vcu118
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#export XILINX_PART := xcvu9p-flga2104-2L-e
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#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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#export board := vcu118
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# vcu108
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#export XILINX_PART := xcvu095-ffva2104-2-e
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#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
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#export board := vcu108
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# Arty A7
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export XILINX_PART := xc7a100tcsg324-1
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export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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export board := ArtyA7
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# for Arty A7 and S7 boards
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all: FPGA_Arty
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# VCU 108 and VCU 118 boards
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#all: FPGA_VCU
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FPGA_Arty: PreProcessFiles IP_Arty
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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FPGA_VCU: PreProcessFiles IP_VCU SDC
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/xlnx_ddr4-$(board).log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log \
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$(dst)/xlnx_axi_crossbar.log \
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$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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$(dst)/xlnx_axi_prtcl_conv.log
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IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/xlnx_ddr3-$(board).log \
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$(dst)/xlnx_mmcm.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log \
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$(dst)/xlnx_axi_crossbar.log \
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$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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$(dst)/xlnx_axi_prtcl_conv.log
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PreProcessFiles:
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rm -rf ../src/CopiedFiles_do_not_add_to_repo/
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cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
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./insert_debug_comment.sh
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$(dst)/%.log: %.tcl
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mkdir -p IP
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cd IP;\
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vivado -mode batch -source ../$*.tcl | tee $*.log
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cleanIP:
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rm -rf IP
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cleanLogs:
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rm -rf *.jou *.log
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cleanFPGA:
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rm -rf WallyFPGA.* reports sim .Xil
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cleanAll: cleanIP cleanLogs cleanFPGA
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