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Author SHA1 Message Date
David Harris
96556064a4 Restored RV64GC BPRED_SIZE=10 for consistent synthesis results 2023-11-17 18:31:44 -08:00
David Harris
423ae2bb76 Ignore benchmark results 2023-11-17 17:02:32 -08:00
David Harris
96f9409da4 Embench Makefile to sweep experiments across configs 2023-11-17 15:11:52 -08:00
David Harris
7b33331cf7 Got Wally sweep running again 2023-11-17 15:10:57 -08:00
David Harris
c500a7c057 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-17 14:26:55 -08:00
David Harris
0eb23569f5 Merge pull request #480 from stineje/main 
wrapper insertion automatically for Wally vs. individual PPA analysis
 2023-11-17 14:26:47 -08:00
James E. Stine
3dc7b93f57 Revert removal of WRAPPER option that is not prudent 2023-11-17 16:25:35 -06:00
David Harris
44ec6efdab Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-17 13:28:07 -08:00
David Harris
f4f389f373 Initial version of embench_arch_sweep.py 2023-11-17 13:27:57 -08:00
David Harris
70c58a8ce1 Merge pull request #484 from ross144/main 
Changed bpred-sim.py to only simulate 12 jobs at once.
 2023-11-17 13:26:24 -08:00
Rose Thompson
8cf2c404bf bpred-sim only simulates 12 jobs at once. 2023-11-17 15:21:58 -06:00
David Harris
8baa5b2e7b Merge pull request #483 from ross144/main 
Fixed branch predictor embench generation results
 2023-11-17 10:07:30 -08:00
Rose Thompson
d95d7130a3 Fixed bugs in paraseHPMC.py 2023-11-17 12:05:22 -06:00
Rose Thompson
38b327eaf8 Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters. 2023-11-17 11:21:25 -06:00
Rose Thompson
0b49c736b9 Removed the size opt tests from the branch predictor analysis. 2023-11-15 22:35:33 -06:00
David Harris
94201e993f Merge pull request #481 from ross144/main 
Fixed the BTB logger so sim_bp correctly reports BTB performance
 2023-11-15 17:45:38 -08:00
Rose Thompson
21b2a71bd6 Updates to btb logger processing. 2023-11-15 16:53:44 -06:00
Rose Thompson
c4f4e0fbc0 Added btb reference data. 2023-11-15 16:39:35 -06:00
Rose Thompson
9a90c15f37 Extended SeparateBranch to support both just branches and all control flow instructions. 2023-11-15 16:36:49 -06:00
Rose Thompson
bc935b1b3b Fixed second bug in the logger script when branch logging enabled but counter logger not. 2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c Fixed bug in the btb branch logging. 
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
 2023-11-15 14:51:47 -06:00
David Harris
7b2bb86ced changed to head of riscv-arch-test 2023-11-15 09:48:13 -08:00
Rose Thompson
dc8502899c Merge pull request #479 from davidharrishmc/main 
Removed and added back in riscv-arch-test to try to fix corruption
 2023-11-15 08:46:42 -08:00
Rose Thompson
663eb9a17d Merge pull request #478 from davidharrishmc/dev 
Removed non-functioning Zfh from rv64gc
 2023-11-15 08:46:24 -08:00
David Harris
eef39bd495 Fixed typo in lsu parameter 2023-11-15 08:30:48 -08:00
David Harris
817ddbc7c5 Adjusted LSU misaligned buffer to fix synthesis warning 2023-11-15 08:19:50 -08:00
David Harris
cfaeeae25a Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter 2023-11-15 08:15:01 -08:00
David Harris
dc3e412c62 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-15 08:06:35 -08:00
David Harris
98176665de Fixed messed-up hazard.sv 2023-11-15 08:05:41 -08:00
James E. Stine
8ca1e3ba37 missing synth.tcl added for use with wrapper 2023-11-15 08:48:07 -06:00
James E. Stine
79d6fe8c93 Add wrapper passing automatically for individual designs vs. Wally 2023-11-15 08:45:25 -06:00
David Harris
20afaa558a Added back in riscv-arch-test 2023-11-15 06:07:57 -08:00
David Harris
1c4b3e37b1 Removed riscv-arch-test submodule that was corrupted 2023-11-15 06:05:55 -08:00
David Harris
90cf128349 Added back riscv-arch-test fresh 2023-11-15 05:48:33 -08:00
David Harris
18c29dd7d0 Removed riscv-arch-test submodule that appears corrupted 2023-11-15 05:46:38 -08:00
David Harris
3308550409 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-14 19:14:03 -08:00
David Harris
77338435ce Merge pull request #476 from naichewa/main 
Final SPI code review
 2023-11-14 19:10:00 -08:00
David Harris
fb135c957c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-14 15:19:22 -08:00
David Harris
5e9157244b Restored Zfh to 0 for rv64gc because it breaks floating-point tests 2023-11-14 15:18:16 -08:00
naichewa
8ffce456bd Merge branch 'spi' into main 2023-11-14 14:51:06 -08:00
naichewa
1ab7c926ea Final Code Review 2023-11-14 13:44:59 -08:00
Rose Thompson
feb45b9b59 Patched up linux imperas testbench. 2023-11-14 14:20:13 -06:00
Rose Thompson
bf51948616 Merge pull request #474 from davidharrishmc/dev 
FP and synthesis cleanup
 2023-11-14 12:03:01 -08:00
Rose Thompson
65356e362a Merge branch 'main' of github.com:ross144/cvw 2023-11-14 13:54:48 -06:00
Rose Thompson
1c54a5698b Modified the device trees to include all the minor extensions. 2023-11-14 13:54:16 -06:00
David Harris
8ba0336c6f Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e 2023-11-14 11:01:58 -08:00
Rose Thompson
efc1d732d8 Fixed the imperas testbench to be compatible with the config changes. 2023-11-14 12:57:44 -06:00
David Harris
5211b3aa85 Merge pull request #473 from ross144/main 
Missed a few files in the last pull request.  Removes the fpga config from the linter.
 2023-11-14 10:15:31 -08:00
Rose Thompson
fdb75203cb Added cbop to to rv32gc. 2023-11-14 10:55:22 -06:00
David Harris
a77bea9954 Merge pull request #472 from ross144/main 
Merge Zicclsm into main branch and removes the FPGA config.  FPGA makefile now automatically creates the config when building
 2023-11-14 08:34:06 -08:00