James E. Stine
59dee5580c
Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
2021-04-01 12:30:37 -05:00
ShreyaSanghai
e33007e30e
added localHistoryPredictor
2021-04-01 22:22:40 +05:30
ushakya22
5d9ed60646
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-01 02:04:57 -04:00
ushakya22
70d272d7e0
d
2021-04-01 02:04:02 -04:00
Shreya Sanghai
65e9747752
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Teo Ene
6aed8eaea1
Updated MISA in coremark_bare config file
2021-03-31 20:39:02 -05:00
Noah Boorstin
4e62c7d5f5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7
busybear: clean up questa warnings
2021-03-31 14:02:15 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
71d76e3b46
Remove virtual memory tests from rv32i folder
2021-03-30 22:51:52 -04:00
Thomas Fleming
9388a9f28a
Disable 'always-on' virtual memory
2021-03-30 22:49:47 -04:00
Thomas Fleming
e35020b7dc
Extend lint-wally to lint both rv32 and rv64
2021-03-30 22:42:28 -04:00
Thomas Fleming
e3d548d452
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3
Update virtual memory tests and move to separate folder
2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7
Add one more test to WALLY-CAUSE, and update privileged testgen
2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58
Add mcause tests to testbench
2021-03-30 17:17:59 -04:00
Domenico Ottolia
ae7868b166
Update privileged tests generator
2021-03-30 16:58:46 -04:00
Domenico Ottolia
47648dc721
Add all working mcause tests
2021-03-30 16:55:12 -04:00
ushakya22
bdd60c7934
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:36:30 -04:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
ushakya22
2b99a7657a
privilege tests
2021-03-30 15:23:47 -04:00
James E. Stine
b2039e5b9a
Second update to divide that didn't get in for some silly git reason
2021-03-30 14:21:45 -05:00
James E. Stine
f4a533b6f6
Initial push of rv64imc and appropriate testbench
2021-03-30 14:21:02 -05:00
Ross Thompson
a3925505bf
fixed some bugs with the RAS.
2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09
Merge branch 'cache2' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 13:32:33 -04:00
Jarred Allen
dd0b3fde59
Comment out failing tests
2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3
Merge branch 'cache' into main
2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 12:55:01 -04:00
David Harris
44ed38fbc8
Added WALLY-PIPELINE to make
2021-03-26 13:13:13 -04:00
David Harris
9f0a58e193
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8
Added fp test to testbench
2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-busybear.sv
2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1
Merge branch 'PPA' into main
...
Conflicts:
wally-pipelined/testbench/testbench-privileged.sv
2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b
removed minor bugs
2021-03-25 20:29:50 -04:00
Jarred Allen
c8a88757ab
Fix error when reading an instruction that crosses a line boundary
2021-03-25 18:47:23 -04:00
ShreyaSanghai
da4086db79
Removed PCW and InstrW from ifu
2021-03-26 01:53:19 +05:30
Jarred Allen
7338ddf853
Remove old icache
2021-03-25 15:46:35 -04:00
Jarred Allen
fa6e6f1724
Works for misaligned instructions not on line boundaries
2021-03-25 15:42:17 -04:00
Noah Boorstin
ee3a53de7a
regression: use busybear batch instead
2021-03-25 15:34:10 -04:00
Domenico Ottolia
9e9fe5e9d3
More bug fixes for privileged tests
2021-03-25 15:05:55 -04:00
Jarred Allen
73d4dd8c15
Begin work on compressed instructions
2021-03-25 14:43:10 -04:00
Noah Boorstin
9eb1786fb1
busybear: quick fix to mem reading
...
also stop ignoring mcause at the start
2021-03-25 14:29:11 -04:00
Brett Mathis
aedc96cd04
FPU Pipeline completed - can begin integration
2021-03-25 13:29:03 -05:00
Domenico Ottolia
fb00d0f209
Fix bugs with privileged tests
2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
David Harris
e5319dfcca
Added WALLY-PIPELINE test to rv64wally
2021-03-25 13:18:50 -04:00
Jarred Allen
feabcf2d50
Make cache output NOP after a reset
2021-03-25 13:18:30 -04:00
