David Harris
bfe8bf3855
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
bbracker
64a3043a88
update wave-do
2021-10-07 19:16:52 -04:00
James E. Stine
739e17ddac
Add generic wave command file
2021-10-06 13:17:49 -05:00
James E. Stine
658dcc8c1b
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
David Harris
9809e57d0c
Replacing XE and DE with SrcAE and SrcBE in divider
2021-10-03 11:11:53 -04:00
David Harris
8f36297569
Added suffixes to more divider signals
2021-10-03 00:32:58 -04:00
David Harris
24bb3f4baf
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
fe69513bb7
Partial divider cleanup
2021-10-02 20:55:37 -04:00
David Harris
d4437b842a
Divider code cleanup
2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d
Moved negating divider otuput to M stage
2021-10-02 10:03:02 -04:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
Ross Thompson
d09b381183
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
b92070a67a
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
eb7b5f1d63
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
bbracker
92ddc9b20a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-15 17:31:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
David Harris
1847198da9
Cleaned up wally-arch test scripts
2021-09-13 00:02:32 -04:00
David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
a31828e925
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
Ross Thompson
5bc90ef32f
Slight modification to wave file.
2021-09-08 10:40:46 -05:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
28fed18421
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
Ross Thompson
00f50184d8
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
bbracker
58d478eb23
restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair
2021-09-04 19:45:04 -04:00
Ross Thompson
5c2deab4e4
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Ross Thompson
4b0344898b
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
de9e234ffa
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
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One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
cbb47956cb
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
642efbb563
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
d2b3b7345e
Moved dcache fsm to separate module.
2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1
Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
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This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
2021-08-25 21:09:42 -05:00
Ross Thompson
c48556836b
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
Ross Thompson
699053bab0
Updated linux test bench documenation and scripts.
2021-08-25 10:54:47 -05:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
c0667f30bb
Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do.
2021-08-19 10:33:11 -05:00
Ross Thompson
4eca94268c
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
15085448d7
Updated linux-wave.do to have cursors at the timer interrupt problem.
2021-08-13 17:29:37 -05:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
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Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
a1c26a16d6
Cleaned up the linux testbench by removing old code and signals.
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Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Ross Thompson
467e24c05c
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee
Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the
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cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
839822d3b1
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
