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Author SHA1 Message Date
Limnanthes Serafini
91fe85486c Log file cleanup 2023-03-29 04:12:10 -07:00
Limnanthes Serafini
0ab06f08c4 Log file cleanup 2023-03-29 04:11:54 -07:00
Limnanthes Serafini
a4d4f0b914 Log file cleanup 2023-03-29 04:11:43 -07:00
Limnanthes Serafini
abf9da3c8b Git issues, repushing 2023-03-29 04:10:47 -07:00
Limnanthes Serafini
7f2ce66a85 A first pass at the Cache simulator. 2023-03-29 04:03:55 -07:00
David Harris
16742cbcb6 Merge pull request #170 from ross144/main 
Fixed issue 148 and problems with i/d cache address loggers.
 2023-03-28 14:32:54 -07:00
Ross Thompson
d0f8db7939 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-28 16:31:50 -05:00
Ross Thompson
84860a062d Modified the testbench to not use the loggers for unsupported configurations. 2023-03-28 16:27:54 -05:00
Ross Thompson
d33f4cfdef Merge branch 'main' of github.com:ross144/cvw 2023-03-28 16:22:26 -05:00
Ross Thompson
c65c9e52d4 Disable loggers by default. 2023-03-28 16:20:45 -05:00
Ross Thompson
650a1a8d7e Now reports if there is a hit or miss. 2023-03-28 16:20:14 -05:00
Ross Thompson
ef26600689 Restored performance counter reports. 2023-03-28 16:15:05 -05:00
Ross Thompson
a5601ea264 Now have logging of i/d cache addresses, but the performance counter reports are x's. 2023-03-28 16:09:54 -05:00
Ross Thompson
65d83b6f63 Merge branch 'main' of github.com:ross144/cvw 2023-03-28 14:47:16 -05:00
Ross Thompson
366a96a0fc Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Ross Thompson
e49cf8a028 Merge pull request #169 from davidharrishmc/dev 
PMP Fix to issue 132
 2023-03-28 11:49:00 -05:00
David Harris
2c8fcc24e0 Fixed bitrot in testfloat tests 2023-03-28 09:35:19 -07:00
David Harris
2427e43ffd Moved rv32 peripheral tests using TEST-LIB to wally32priv because rv32imc doesn't support PMP 2023-03-28 09:08:48 -07:00
David Harris
2e5c50e24a Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
e8904411ce Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
David Harris
4594dffc7f Set PMP to allow all user/supervisor accesses in WALLY-init-lib 2023-03-28 06:46:11 -07:00
David Harris
f24a9be4dc Merge pull request #168 from AlecVercruysse/makecoverage 
Add tests/coverage/ tests as a target to sim/Makefile
 2023-03-28 05:23:04 -07:00
David Harris
cce4d06f53 Merge pull request #167 from ross144/main 
Added clarificaiton to buildroot linux testvector generation
 2023-03-28 05:21:44 -07:00
David Harris
2e238c15aa CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
Ross Thompson
514738ad96 Now reports i cache and d cache memory accesses. 2023-03-27 23:44:50 -05:00
Ross Thompson
03666dab1c Merge pull request #166 from magpyed/patch-1 
Fixing order of local repo commands in README
 2023-03-27 22:41:20 -05:00
Ross Thompson
3150d9244d Merge branch 'main' of github.com:ross144/cvw 2023-03-27 18:37:07 -05:00
Ross Thompson
059c73a4d2 First stab at the i cache logger. 2023-03-27 18:36:51 -05:00
Ross Thompson
4062038848 Added some additional details about the buildroot install. 2023-03-27 18:06:20 -05:00
Alec Vercruysse
a7066a20f1 add tests/coverage/ tests as a target to sim/Makefile 2023-03-27 14:02:30 -07:00
Limnanthes Serafini
aaba728dd7 Fixing order of local repo commands in README 2023-03-27 13:35:48 -07:00
David Harris
383f76a5c5 Merge pull request #163 from ross144/main 
updated GPIO signal names to match book.
 2023-03-27 12:47:00 -07:00
Ross Thompson
67ddce4a6b Added buildroot instructions back to readme. moved these instructions to the docs directory. 2023-03-27 14:45:55 -05:00
Ross Thompson
d91188c86e Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 11:55:19 -05:00
Ross Thompson
9092dcb866 Merge pull request #165 from davidharrishmc/dev 
Imperas linux merge
 2023-03-27 11:54:30 -05:00
David Harris
9b7e5cec1f Removed unnecessary monitor 2023-03-27 09:52:38 -07:00
Ross Thompson
d9691c1542 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-27 10:22:48 -05:00
David Harris
a0504fd70c Commented out setting RISCV in run-imperas-linux.sh 2023-03-27 06:34:45 -07:00
David Harris
0ac4fd493a Merge pull request #164 from eroom1966/add-linux 
Add linux
 2023-03-27 06:26:41 -07:00
eroom1966
1a10e48ecf update to allow running of ImperasDV with linux boot 
optimize performance of the tracer
 2023-03-27 09:46:16 +01:00
Lee Moore
4bb7dadc00 Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
Ross Thompson
1986ef0625 Started constrains file for arty a7 fpga. 2023-03-24 20:38:13 -05:00
Ross Thompson
ca4b058373 Modified plic and uart to remove async reset. This removes vivado critical warning. 2023-03-24 20:37:48 -05:00
Ross Thompson
576d37eb8c Updated fpga constraints to remove critical warning. 2023-03-24 19:09:36 -05:00
Ross Thompson
0afba56927 Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Ross Thompson
af8f1fd036 Renamed controllerinputstage to controllerinput to match book. 2023-03-24 17:57:02 -05:00
Ross Thompson
6e3d4999a7 Merge pull request #162 from davidharrishmc/dev 
Merging spaces
 2023-03-24 17:49:26 -05:00
David Harris
0b0d954e7f Merged ross's spacing fixes 2023-03-24 15:47:26 -07:00
David Harris
092d34373f Merge pull request #159 from ross144/main 
Renamed signal to match book
 2023-03-24 15:34:59 -07:00
Ross Thompson
46b1bca4fc Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00