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Merge pull request from ross144/main

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Added clarificaiton to buildroot linux testvector generation
This commit is contained in:
David Harris 2023-03-28 05:21:44 -07:00 committed by GitHub
commit cce4d06f53
2 changed files with 52 additions and 1 deletions

1
docs/README-linux.md
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@ -16,6 +16,7 @@ To configure and build Buildroot:
$ make --jobs
To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb.
Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories.
$ source ~/riscv-wally/setup.sh
$ cd $WALLY/linux/buildroot-scripts

52
testbench/testbench.sv
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@ -30,6 +30,8 @@
`define PrintHPMCounters 1
`define BPRED_LOGGER 1
`define I_CACHE_ADDR_LOGGER 1
`define D_CACHE_ADDR_LOGGER 1
module testbench;
parameter DEBUG=0;
@ -546,9 +548,57 @@ logic [3:0] dummy;
end
end
end
end
if (`I_CACHE_ADDR_LOGGER == 1) begin
int file;
string LogFile;
logic resetD, resetEdge;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = $psprintf("ICache.log");
file = $fopen(LogFile, "w");
end
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(~dut.core.StallD & ~dut.core.FlushD) begin
$fwrite(file, "%h R\n", dut.core.ifu.PCPF);
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
end
if (`D_CACHE_ADDR_LOGGER == 1) begin
int file;
string LogFile;
logic resetD, resetEdge;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = $psprintf("DCache.log");
file = $fopen(LogFile, "w");
end
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin
$fwrite(file, "%h R\n", dut.core.lsu.PAdrM);
end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin
$fwrite(file, "%h W\n", dut.core.lsu.PAdrM);
end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change
$fwrite(file, "%h A\n", dut.core.lsu.PAdrM);
end else if (dut.core.lsu.bus.dcache.FlushDCache) begin
$fwrite(file, "%h F\n", dut.core.lsu.PAdrM);
end
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
end
if (`BPRED_SUPPORTED == 1) begin
if (`BPRED_LOGGER) begin
string direction;