mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #163 from ross144/main
updated GPIO signal names to match book.
This commit is contained in:
David Harris
GitHub
commit
383f76a5c5
40
docs/README-linux.md
Normal file
40
docs/README-linux.md
Normal file
@ -0,0 +1,40 @@
|
||||
### Cross-Compile Buildroot Linux
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||||
|
||||
Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details.
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||||
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||||
Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot.
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||||
|
||||
To configure and build Buildroot:
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||||
|
||||
$ cd $RISCV
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$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now
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$ git clone https://github.com/buildroot/buildroot.git
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$ cd buildroot
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$ git checkout 2021.05 # last tested working version
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||||
$ cp -r $WALLY/linux/buildroot-config-src/wally ./board
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$ cp ./board/wally/main.config .config
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$ make --jobs
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To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb.
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||||
$ source ~/riscv-wally/setup.sh
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$ cd $WALLY/linux/buildroot-scripts
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$ make all
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Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images.
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### Generate load images for linux boot
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||||
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||||
The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors
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cd cvw/linux/testvector-generation
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./genInitMem.sh
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||||
This may require changing file permissions to the linux-testvectors directory.
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||||
### Generate QEMU linux trace
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The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours.
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||||
cd cvw/linux/testvector-generation
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./genTrace.sh
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||||
251
fpga/constraints/constraints-artyA7.xdc
Normal file
251
fpga/constraints/constraints-artyA7.xdc
Normal file
@ -0,0 +1,251 @@
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# The main clocks are all autogenerated by the Xilinx IP
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# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
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# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
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# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
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||||
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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##### GPI ####
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set_property PACKAGE_PIN D9 [get_ports {GPI[0]}]
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set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
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set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
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set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 10.000
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##### GPO ####
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set_property PACKAGE_PIN G6 [get_ports {GPO[0]}]
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set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
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set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
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set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
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set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
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set_max_delay -to [get_ports {GPO[*]}] 10.000
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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# *** IOSTANDARD is probably wrong
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set_property PACKAGE_PIN A9 [get_ports UARTSin]
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set_property PACKAGE_PIN D0 [get_ports UARTSout]
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set_max_delay -from [get_ports UARTSin] 10.000
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set_max_delay -to [get_ports UARTSout] 10.000
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
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set_property IOSTANDARD LVCMOS3 [get_ports UARTSout]
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set_property DRIVE 6 [get_ports UARTSout]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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#************** reset is inverted
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set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
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set_max_delay -from [get_ports reset] 15.000
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set_false_path -from [get_ports reset]
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set_property PACKAGE_PIN C2 [get_ports {reset}]
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set_property IOSTANDARD LVCMOS33 [get_ports {reset}]
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##### cpu_reset #####
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# ***********
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set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
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set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
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##### calib #####
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# **********
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set_property PACKAGE_PIN BA37 [get_ports calib]
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set_property IOSTANDARD LVCMOS12 [get_ports calib]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
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set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
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##### ahblite_resetn #####
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# ***************
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set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
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set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
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##### south_rst #####
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# ***********************
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set_property PACKAGE_PIN BE22 [get_ports south_rst]
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set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
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##### SD Card I/O #####
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#***** may have to switch to Pmod JB or JC.
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set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
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set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
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set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
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set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
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set_property PACKAGE_PIN F2 [get_ports SDCCLK]
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set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
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set_property PULLUP true [get_ports {SDCDat[3]}]
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set_property PULLUP true [get_ports {SDCDat[2]}]
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set_property PULLUP true [get_ports {SDCDat[1]}]
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set_property PULLUP true [get_ports {SDCDat[0]}]
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set_property PULLUP true [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
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||||
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set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
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# *********************************
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set_property DCI_CASCADE {64} [get_iobanks 65]
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set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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# ddr3
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
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||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
|
||||
|
||||
|
||||
set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
|
||||
set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
|
||||
set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
|
||||
set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
|
||||
set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
|
||||
set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
|
||||
set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
|
||||
set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
|
||||
set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
|
||||
set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
|
||||
set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
|
||||
set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
|
||||
set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
|
||||
set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
|
||||
set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
|
||||
set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
|
||||
set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
|
||||
set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
|
||||
set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
|
||||
set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
|
||||
set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
|
||||
set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
|
||||
set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
|
||||
set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
|
||||
set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
|
||||
set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
|
||||
set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
|
||||
set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
|
||||
set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
|
||||
set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
|
||||
set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
|
||||
set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
|
||||
set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
|
||||
set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
|
||||
set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
|
||||
set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
|
||||
set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
|
||||
set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
|
||||
set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
|
||||
set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
|
||||
set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
|
||||
set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n]
|
||||
set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n]
|
||||
set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n]
|
||||
set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n]
|
||||
set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
|
||||
set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
|
||||
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
|
||||
|
||||
|
||||
|
||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
|
||||
set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
|
||||
|
||||
|
||||
@ -120,8 +120,6 @@ ebu/ebu.sv: logic HCLK
|
||||
ebu/ebu.sv: logic HREADY
|
||||
ebu/ebu.sv: logic HRESP
|
||||
ebu/ebu.sv: logic HADDR
|
||||
ebu/ebu.sv: logic HWDATA
|
||||
ebu/ebu.sv: logic HWSTRB
|
||||
ebu/ebu.sv: logic HWRITE
|
||||
ebu/ebu.sv: logic HSIZE
|
||||
ebu/ebu.sv: logic HBURST
|
||||
|
||||
@ -88,7 +88,7 @@ module fpgaTop
|
||||
|
||||
|
||||
|
||||
wire [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
wire [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
|
||||
wire SDCCmdIn;
|
||||
wire SDCCmdOE;
|
||||
@ -183,8 +183,8 @@ module fpgaTop
|
||||
|
||||
|
||||
|
||||
assign GPIOPinsIn = {28'b0, GPI};
|
||||
assign GPO = GPIOPinsOut[4:0];
|
||||
assign GPIOIN = {28'b0, GPI};
|
||||
assign GPO = GPIOOUT[4:0];
|
||||
assign ahblite_resetn = peripheral_aresetn;
|
||||
assign cpu_reset = bus_struct_reset;
|
||||
assign calib = c0_init_calib_complete;
|
||||
@ -231,9 +231,9 @@ module fpgaTop
|
||||
.HMASTLOCK(HMASTLOCK),
|
||||
.HREADY(HREADY),
|
||||
// GPIO
|
||||
.GPIOPinsIn(GPIOPinsIn),
|
||||
.GPIOPinsOut(GPIOPinsOut),
|
||||
.GPIOPinsEn(GPIOPinsEn),
|
||||
.GPIOIN(GPIOIN),
|
||||
.GPIOOUT(GPIOOUT),
|
||||
.GPIOEN(GPIOEN),
|
||||
// UART
|
||||
.UARTSin(UARTSin),
|
||||
.UARTSout(UARTSout),
|
||||
|
||||
@ -33,7 +33,7 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module controllerinputstage #(
|
||||
module controllerinput #(
|
||||
parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs
|
||||
)(
|
||||
input logic HCLK,
|
||||
@ -98,14 +98,14 @@ module ebu (
|
||||
// input stages and muxing for IFU and LSU
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
|
||||
controllerinput IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
|
||||
.Request(IFUReq),
|
||||
.HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
|
||||
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
|
||||
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
|
||||
|
||||
// LSU always has priority so there should never be a need to save and restore the address phase inputs.
|
||||
controllerinputstage #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
|
||||
controllerinput #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
|
||||
.Request(LSUReq),
|
||||
.HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
|
||||
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
|
||||
|
||||
@ -41,8 +41,8 @@ module gpio_apb (
|
||||
output logic [`XLEN-1:0] PRDATA,
|
||||
output logic PREADY,
|
||||
input logic [31:0] iof0, iof1,
|
||||
input logic [31:0] GPIOPinsIn,
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
|
||||
input logic [31:0] GPIOIN,
|
||||
output logic [31:0] GPIOOUT, GPIOEN,
|
||||
output logic GPIOIntr
|
||||
);
|
||||
|
||||
@ -138,8 +138,8 @@ module gpio_apb (
|
||||
|
||||
// chip i/o
|
||||
// connect OUT to IN for loopback testing
|
||||
if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en;
|
||||
else assign input0d = GPIOPinsIn & input_en;
|
||||
if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en;
|
||||
else assign input0d = GPIOIN & input_en;
|
||||
|
||||
// synchroninzer for inputs
|
||||
flop #(32) sync1(PCLK,input0d,input1d);
|
||||
@ -148,8 +148,8 @@ module gpio_apb (
|
||||
assign input_val = input3d;
|
||||
assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0
|
||||
assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
|
||||
assign GPIOPinsOut = gpio_out ^ out_xor; // per-bit flip output polarity
|
||||
assign GPIOPinsEn = output_en;
|
||||
assign GPIOOUT = gpio_out ^ out_xor; // per-bit flip output polarity
|
||||
assign GPIOEN = output_en;
|
||||
|
||||
assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
|
||||
endmodule
|
||||
|
||||
@ -97,7 +97,7 @@ module plic_apb (
|
||||
// ==================
|
||||
// Register Interface
|
||||
// ==================
|
||||
always @(posedge PCLK,negedge PRESETn) begin
|
||||
always @(posedge PCLK) begin
|
||||
// resetting
|
||||
if (~PRESETn) begin
|
||||
intPriority <= #1 {`N{3'b0}};
|
||||
|
||||
@ -290,7 +290,7 @@ module uartPC16550D(
|
||||
assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
|
||||
|
||||
// receive FIFO and register
|
||||
always_ff @(posedge PCLK, negedge PRESETn)
|
||||
always_ff @(posedge PCLK)
|
||||
if (~PRESETn) begin
|
||||
rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0;
|
||||
end else begin
|
||||
|
||||
@ -51,8 +51,8 @@ module uncore (
|
||||
output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT
|
||||
output logic MExtInt, SExtInt, // External interrupts from PLIC
|
||||
output logic [63:0] MTIME_CLINT, // MTIME, from CLINT
|
||||
input logic [31:0] GPIOPinsIn, // GPIO pin input value
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable
|
||||
input logic [31:0] GPIOIN, // GPIO pin input value
|
||||
output logic [31:0] GPIOOUT, GPIOEN, // GPIO pin output value and enable
|
||||
input logic UARTSin, // UART serial input
|
||||
output logic UARTSout, // UART serial output
|
||||
output logic SDCCmdOut, // SD Card command output
|
||||
@ -133,9 +133,9 @@ module uncore (
|
||||
gpio_apb gpio(
|
||||
.PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||
.PRDATA(PRDATA[0]), .PREADY(PREADY[0]),
|
||||
.iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr);
|
||||
.iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr);
|
||||
end else begin : gpio
|
||||
assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
|
||||
assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0;
|
||||
end
|
||||
if (`UART_SUPPORTED == 1) begin : uart
|
||||
uart_apb uart(
|
||||
|
||||
@ -51,9 +51,9 @@ module wallypipelinedsoc (
|
||||
output logic HREADY,
|
||||
// I/O Interface
|
||||
input logic TIMECLK, // optional for CLINT MTIME counter
|
||||
input logic [31:0] GPIOPinsIn, // inputs from GPIO
|
||||
output logic [31:0] GPIOPinsOut, // output values for GPIO
|
||||
output logic [31:0] GPIOPinsEn, // output enables for GPIO
|
||||
input logic [31:0] GPIOIN, // inputs from GPIO
|
||||
output logic [31:0] GPIOOUT, // output values for GPIO
|
||||
output logic [31:0] GPIOEN, // output enables for GPIO
|
||||
input logic UARTSin, // UART serial data input
|
||||
output logic UARTSout, // UART serial data output
|
||||
input logic SDCCmdIn, // SDC Command input
|
||||
@ -85,7 +85,7 @@ module wallypipelinedsoc (
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
|
||||
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin,
|
||||
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin,
|
||||
.UARTSout, .MTIME_CLINT,
|
||||
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
|
||||
end
|
||||
|
||||
@ -263,8 +263,8 @@ module testbench;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic [31:0] GPIOPinsIn;
|
||||
logic [31:0] GPIOPinsOut, GPIOPinsEn;
|
||||
logic [31:0] GPIOIN;
|
||||
logic [31:0] GPIOOUT, GPIOEN;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
// FPGA-specific Stuff
|
||||
@ -430,7 +430,7 @@ module testbench;
|
||||
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
|
||||
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK,
|
||||
.TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout,
|
||||
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
||||
|
||||
|
||||
@ -252,8 +252,8 @@ module testbench;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic [31:0] GPIOPinsIn;
|
||||
logic [31:0] GPIOPinsOut, GPIOPinsEn;
|
||||
logic [31:0] GPIOIN;
|
||||
logic [31:0] GPIOOUT, GPIOEN;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
// FPGA-specific Stuff
|
||||
@ -264,7 +264,7 @@ module testbench;
|
||||
logic [3:0] SDCDatIn;
|
||||
|
||||
// Hardwire UART, GPIO pins
|
||||
assign GPIOPinsIn = 0;
|
||||
assign GPIOIN = 0;
|
||||
assign UARTSin = 1;
|
||||
|
||||
// Wally
|
||||
@ -272,7 +272,7 @@ module testbench;
|
||||
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
|
||||
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK,
|
||||
.TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout,
|
||||
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
||||
|
||||
|
||||
@ -150,7 +150,7 @@ logic [3:0] dummy;
|
||||
string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
|
||||
integer outputFilePointer;
|
||||
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
logic SDCCLK;
|
||||
@ -169,7 +169,7 @@ logic [3:0] dummy;
|
||||
logic InReset;
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOPinsIn = 0;
|
||||
assign GPIOIN = 0;
|
||||
assign UARTSin = 1;
|
||||
|
||||
if(`EXT_MEM_SUPPORTED) begin
|
||||
@ -199,7 +199,7 @@ logic [3:0] dummy;
|
||||
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
// Track names of instructions
|
||||
|
||||
@ -73,7 +73,7 @@ module testbench;
|
||||
string testName;
|
||||
string memfilename, testDir, adrstr, elffilename;
|
||||
|
||||
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
|
||||
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
logic SDCCLK;
|
||||
@ -217,7 +217,7 @@ module testbench;
|
||||
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOPinsIn = 0;
|
||||
assign GPIOIN = 0;
|
||||
assign UARTSin = 1;
|
||||
|
||||
if(`EXT_MEM_SUPPORTED) begin
|
||||
@ -247,7 +247,7 @@ module testbench;
|
||||
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
// Track names of instructions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user