Kip Macsai-Goren
1b2822e078
added support for sv48 and some docs on how to use these files
2021-06-03 14:32:12 -04:00
Kip Macsai-Goren
a84dd6dfc5
added tests for SV48 and translation off with vmem
2021-06-03 14:28:52 -04:00
bbracker
d8913e5547
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-03 10:03:26 -04:00
bbracker
8338b3bd34
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
bbracker
987460c49a
reached a good stopping point on buildroot progress; parse_qemu.py has been rewritten for readability and QEMU MMU failure workaround
2021-06-03 10:00:16 -04:00
Ross Thompson
db2a38c300
Fixed a few lint errors,
...
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
bbracker
4f03ecb6ec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-02 10:03:23 -04:00
bbracker
28abd28b1f
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
f7deda0514
implemented Sv48.
2021-06-01 17:50:37 -04:00
Kip Macsai-Goren
06cf3a8403
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
James E. Stine
7f5e5287b0
delete div.bak
2021-06-01 17:39:54 -04:00
Ross Thompson
2093e7cce3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 15:20:37 -05:00
Ross Thompson
7afbd8d877
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
James E. Stine
2c140679e3
Minor cosmetic update to fpu.sv
2021-06-01 15:45:32 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
8e330367ac
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
605ceb7ddb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
f5aa5d7c67
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
8f7e69715d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
9a49cf74c3
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
8f9680556f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
1db8d0e59c
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
42af5f9818
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
a71b97e878
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
2f365a9e07
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
889b935630
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
529226ac8d
made priority encoder parameterizable
2021-05-28 18:09:28 -04:00
Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Katherine Parry
0646e08609
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Ross Thompson
668a79cf77
Updated benchmarking code.
2021-05-27 11:48:29 -05:00
Katherine Parry
bd05de0dbb
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
James E. Stine
e3b3321f91
delete old file for FPregfile
2021-05-26 09:13:09 -05:00
James E. Stine
cc2a7ced7f
Add regression test for fpadd
2021-05-26 09:12:37 -05:00
Katherine Parry
3869a73a9c
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
Kip Macsai-Goren
d74803701b
completed mstatus test for rv32p, rv64p, updated testbench to reflect
2021-05-25 15:44:52 -04:00
Kip Macsai-Goren
32923cb250
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-25 15:28:19 -04:00
Ross Thompson
735e511073
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
James E. Stine
e32e812f6a
Update FPregfile to use more compact code and better structure for ease in reading
2021-05-25 13:21:59 -05:00
Ross Thompson
aa9a81b760
Merge remote-tracking branch 'refs/remotes/origin/main' into main
2021-05-24 23:25:36 -05:00
Ross Thompson
13034c7406
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
Kip Macsai-Goren
ba134eb166
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
2021-05-24 20:59:26 -04:00
James E. Stine
bbc1dfb309
Minor cosmetic elements on div.sv
2021-05-24 19:30:28 -05:00
James E. Stine
1704fdc877
Mod for DIV/REM instruction and update to div.sv unit
2021-05-24 19:29:13 -05:00
bbracker
82a6ee4c0e
slightly more path independence for using verilator
2021-05-24 18:11:56 -04:00
bbracker
d7405e476e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-24 17:09:14 -04:00
bbracker
7e2073e482
peripheral testing standardization
2021-05-24 17:08:40 -04:00
