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Configurable RISC-V Processor
895 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
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2f365a9e07
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James E. Stine 2f365a9e07 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
riscv-coremark commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
wally-pipelined Add enhancements to integer divider including: 2021-05-31 09:12:21 -04:00
.gitignore script for running make and logging output 2021-05-17 22:12:18 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor