David Harris
8a55935456
simplified fma Makefile
2022-02-26 19:55:42 +00:00
David Harris
1852eccaab
Made softfloat.a a symlink
2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac
Added start of fma
2022-02-26 19:51:19 +00:00
David Harris
eda60a7691
Moved Softfloat / TestFloat
2022-02-26 19:17:32 +00:00
Ross Thompson
97d64201f7
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
d331b9f29d
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
Ross Thompson
6a52f95cc8
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c
fix lint bugs in PLIC and UART
2022-02-22 05:04:18 +00:00
bbracker
a6047697c3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
bbracker
e7934c585a
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
a6e83a2ca2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 12:46:22 -06:00
Ross Thompson
56fc6d0d7c
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
ushakya22
67780305ae
Moved order of reading a, b, and result from test vectors file so that result
...
matches up with inputs a and b
2022-02-21 17:28:11 +00:00
ushakya22
88060a74f5
- created new testbench file instead of having it at the bottom of the srt file
...
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench
Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
2022-02-21 16:24:50 +00:00
ushakya22
d1089163a9
- Created exponent divsion module
...
- top module includes exponent module now
Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
2022-02-21 16:13:30 +00:00
ushakya22
c6bd51a707
Changed Makefile to compile exptestgen instead of testgen
2022-02-21 16:08:45 +00:00
ushakya22
08d997d68b
reverted srt_standford back to original file pre modifications by Udeema
2022-02-21 16:08:09 +00:00
ushakya22
1495f6ac70
verilator lint for srt
2022-02-21 16:05:43 +00:00
ushakya22
5b83ad0929
Created test vector generation file for exponent and mantissa division
2022-02-21 16:04:41 +00:00
Ross Thompson
f48b12b089
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
cbf4395457
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
d1578d8356
added scratch register tests for 64 and 32 bits
2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
5bdb612567
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-21 00:34:54 +00:00
Ross Thompson
ae06785b9f
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
20a5798f43
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
6a0ffff05d
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
4113d64b19
added 32 bit pma tests to regression even though they've been working fo a while
2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
c3523dfa15
Added misa test for both 32 and 64 bits
2022-02-18 19:41:50 +00:00
Ross Thompson
6cd9d84e7f
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
ad237b3ce5
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
cbac34943c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
f3c7025ade
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
