David Harris
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0abfe5cb55
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Fixed some lint errors in derived configs
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2024-01-31 11:39:59 -08:00 |
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David Harris
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f37c7bb1f6
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Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
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2024-01-30 06:27:18 -08:00 |
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David Harris
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da4eca4854
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Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
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2024-01-15 13:24:57 -08:00 |
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David Harris
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9eb6d9c8b8
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Added Zicond support
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2024-01-11 07:37:15 -08:00 |
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Rose Thompson
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5062a8c89c
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Added parameter for cache's SRAM length.
Progress towards verilator support.
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2023-12-18 12:50:49 -06:00 |
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David Harris
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a77bea9954
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Merge pull request #472 from ross144/main
Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building
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2023-11-14 08:34:06 -08:00 |
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Rose Thompson
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95fc5f4a1c
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
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David Harris
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d5ba8fc5e6
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fdivsqrt parameter cleanup
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2023-11-10 18:33:08 -08:00 |
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David Harris
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3cae2385ab
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Simplified out LOGRK parameter
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2023-11-10 18:19:41 -08:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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David Harris
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953c53d065
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fdivsqrt parameter cleanup
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2023-11-10 09:11:15 -08:00 |
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Rose Thompson
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0a4ed5515b
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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Rose Thompson
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657409aec5
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Addec ZICCLSM to config files and started on lsu instance.
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2023-10-27 13:07:23 -05:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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28752303be
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Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
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2023-10-04 12:28:12 -07:00 |
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Ross Thompson
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f863cbf366
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Actually fixed non-power of 2 issue with RAS.
Added RAS swapping to branch predictor scripts and configurations.
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2023-09-27 12:25:05 -05:00 |
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Kevin Kim
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dabd15e029
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synth works
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2023-08-26 21:11:21 -07:00 |
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David Harris
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c6631ef808
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Added N and PBMT bits to MMU PTE
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2023-08-24 19:44:46 -07:00 |
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Ross Thompson
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b1f7a5768f
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Removed all old references to the old flash card controller.
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
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2023-07-24 15:45:57 -05:00 |
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Ross Thompson
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a89a1e675c
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Merge branch 'boot' into mergeBoot
Merges Jacob's new sdc controller into wally.
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2023-07-21 17:43:45 -05:00 |
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Ross Thompson
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af0e33209f
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Removed QEMU from configurations.
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2023-07-19 10:23:55 -05:00 |
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Ross Thompson
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b756b248b4
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Wow. The newest version of Vivado does not like the enums as parameters.
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
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2023-07-18 15:07:10 -05:00 |
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David Harris
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644afa16cd
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Clean up privilege rs1 decoding and implement svinval as sfence.vma
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2023-07-13 02:41:17 -07:00 |
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Ross Thompson
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d2219023c3
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 14:57:23 -05:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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David Harris
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6a0d818d74
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Other Wally cleanup
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2023-06-09 09:37:09 -07:00 |
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Ross Thompson
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1ceea51d8b
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Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
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2023-05-31 16:51:00 -05:00 |
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Ross Thompson
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a963f0af3a
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Updated source code to be compatible with verilator 5.011 for lint only.
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2023-05-31 10:44:23 -05:00 |
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Ross Thompson
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1315a0bf4a
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Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
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2023-05-26 16:00:14 -05:00 |
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Ross Thompson
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930fb67308
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Trying to figure out why the parameterization slowed down modelsim so much.
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2023-05-24 12:44:42 -05:00 |
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