Ross Thompson
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ab1af0fabf
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2024-06-19 09:25:39 -07:00 |
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David Harris
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10e6d5846b
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Removed unnecessary Umfirst from early termination
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2024-06-19 09:18:51 -07:00 |
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David Harris
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4b4980e42d
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Fixed undriven OutFmt
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2024-06-19 09:17:32 -07:00 |
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David Harris
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54cb612577
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Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU
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2024-06-19 07:48:54 -07:00 |
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David Harris
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1f569ed6f8
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Merge pull request #838 from jordancarlin/vcs_fix
Update VCS RTL file exclusions with renamed ram
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2024-06-19 05:29:40 -07:00 |
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Jordan Carlin
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156bfc0387
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Update f_fma tests to use smaller files from riscv-arch-test
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2024-06-18 23:38:03 -07:00 |
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Jordan Carlin
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569ccfd829
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Update riscv-arch-test submodule
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2024-06-18 23:34:02 -07:00 |
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Jordan Carlin
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d58b454a8b
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Finish switching Zfa to use riscv-arch-test
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2024-06-18 23:31:37 -07:00 |
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Jordan Carlin
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00ccd80479
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Update VCS RTL file exclusions with renamed ram
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2024-06-18 22:47:00 -07:00 |
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Jordan Carlin
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955f5d831f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-06-18 22:39:05 -07:00 |
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Ross Thompson
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2581ea0b74
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Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.
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2024-06-18 16:48:49 -07:00 |
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Rose Thompson
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d2933edee4
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Merge pull request #836 from davidharrishmc/dev
Code Cleanup: Lint Improvements
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2024-06-18 08:56:17 -07:00 |
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David Harris
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301ded05f8
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Unused signal cleanup
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2024-06-18 08:15:48 -07:00 |
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David Harris
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cb563e8018
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Clean up unused signals
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2024-06-18 08:07:14 -07:00 |
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Ross Thompson
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00e0549c36
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I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word.
The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.
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2024-06-18 07:44:19 -07:00 |
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David Harris
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c1fd7a9589
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Removed unused signals
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2024-06-18 07:28:52 -07:00 |
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Jordan Carlin
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a493b9b131
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Merge pull request #835 from davidharrishmc/dev
Fixed Issue #752 of Verilator simulation by changing LRUMemory to be …
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2024-06-18 07:27:35 -07:00 |
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David Harris
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8bae52b09d
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Lint cleanup of unused signals
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2024-06-18 06:49:17 -07:00 |
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David Harris
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45f505250c
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Lint cleanup
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2024-06-18 06:23:43 -07:00 |
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David Harris
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3fa37b0233
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Lint cleanup
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2024-06-18 06:15:17 -07:00 |
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David Harris
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cac67aae4f
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Lint cleanup
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2024-06-18 05:58:54 -07:00 |
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David Harris
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ecae1100f6
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Lint cleanup
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2024-06-18 05:49:49 -07:00 |
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David Harris
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7509e856df
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Removed asynchronous reset causing lint issue in peripherals
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2024-06-18 05:49:12 -07:00 |
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David Harris
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2fc9edff45
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Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly
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2024-06-18 04:40:38 -07:00 |
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Ross Thompson
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93829ce509
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Success! We have some instructions comparing across the FPGA and IDV!
However I'm still losing ethernet frames.
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2024-06-17 13:41:40 -07:00 |
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Ross Thompson
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598770da51
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Getting much closer to a working version.
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2024-06-17 12:37:10 -07:00 |
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Ross Thompson
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cccb40e4b5
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Got the tracer not overrunning ethernet buffers so frames are not being dropped.
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2024-06-17 09:16:24 -07:00 |
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Ross Thompson
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82b54c0887
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Got IDV properly initalized.
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2024-06-17 09:15:59 -07:00 |
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Rose Thompson
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54c07265ba
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Merge pull request #833 from davidharrishmc/dev
Code cleanup in anticipation of code review
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2024-06-14 21:06:47 -07:00 |
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David Harris
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4a4bbdfc43
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More code cleanup
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2024-06-14 09:50:07 -07:00 |
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David Harris
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bfd3c9fe86
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Fixed gettenvval when variable is undefined per verilator Issue 5179
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2024-06-14 07:09:53 -07:00 |
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David Harris
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53477b2c85
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Code cleanup
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2024-06-14 07:08:17 -07:00 |
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David Harris
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8f09240e6c
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Simplified outdated documentation pointers
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2024-06-14 03:42:15 -07:00 |
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David Harris
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b1c9450b4a
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Code cleanup: RAM, fdivsqrt
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2024-06-14 03:35:05 -07:00 |
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David Harris
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6789f32154
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Starting code cleanup
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2024-06-14 02:54:43 -07:00 |
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David Harris
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334b616d6f
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Removed redundant apt-get line
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2024-06-14 02:52:27 -07:00 |
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David Harris
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fb75fe461c
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Remove stale questa wkdir before regression
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2024-06-14 02:51:55 -07:00 |
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Ross Thompson
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47523c97ac
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Getting closer to figuring out the lost ethernet frame bugs.
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2024-06-13 15:46:54 -07:00 |
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Rose Thompson
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b77fcd70e6
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-06-13 13:58:07 -05:00 |
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Ross Thompson
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c9f51df34a
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Fixed bug in rvvi reset.
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2024-06-12 14:47:32 -07:00 |
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Ross Thompson
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323dbd348e
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Progress.
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2024-06-12 12:54:21 -07:00 |
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Ross Thompson
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f5d4db68b1
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Modified rvvidaemon to populate a struct with all the relavent fields.
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2024-06-12 08:56:16 -07:00 |
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David Harris
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312c9c9f55
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Updated logger to new IClass signal name
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2024-06-12 07:24:05 -07:00 |
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David Harris
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28142eff64
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Formatting shiftcorrection
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2024-06-12 04:25:13 -07:00 |
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David Harris
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544aa7cd8d
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shiftcorrection cleanup
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2024-06-12 04:13:51 -07:00 |
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David Harris
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b7e2f34966
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shiftcorrection cleanup
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2024-06-12 03:59:55 -07:00 |
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Ross Thompson
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3e7d07dfb6
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Better.
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2024-06-11 17:14:59 -07:00 |
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Ross Thompson
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8bce2fc739
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Getting closer.
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2024-06-11 16:21:53 -07:00 |
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Ross Thompson
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c9f3da51cb
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getting closer to full reconstruction of rvvi.
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2024-06-11 15:35:35 -07:00 |
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Ross Thompson
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3d9f796f21
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Better parsing of rvvi.
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2024-06-11 14:36:34 -07:00 |
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