140 Commits

Author	SHA1	Message	Date
Ross Thompson	85dbec5969	Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.	2022-08-21 15:28:29 -05:00
Ross Thompson	2ba390adf4	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00
Ross Thompson	f6e5746e59	Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.	2022-08-17 16:09:20 -05:00
Ross Thompson	413a9bf58b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
Ross Thompson	57fcf0ef79	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
Ross Thompson	3cd8404917	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
Katherine Parry	1bd6351e1f	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
Ross Thompson	40e7cda84a	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
Ross Thompson	719b00e338	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	cd68896637	Merged evict dirty clear with flush write back.	2022-07-24 00:22:43 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	17ae1a1b1b	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Ross Thompson	1cad05fef9	Minor cleanup of cache.	2022-07-19 23:04:23 -05:00
Ross Thompson	8698799077	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Ross Thompson	0ef6137ab9	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	8356e5d742	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
Katherine Parry	18d7fee541	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
David Harris	03a20610aa	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
David Harris	d1a7832dd9	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	97e7e619d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
James Stine	99fed5d59f	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	425fec0f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	c581fba4aa	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	f865994ba1	fixing port errors	2022-07-07 21:57:10 +00:00
Katherine Parry	7771f7b3eb	added load and store test	2022-07-07 21:48:51 +00:00
David Harris	f2915129ab	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
Ross Thompson	d716c25275	Fixed an issue with direct map cache's nextway logic. ... Also found a small error in the replacement policy.	2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye	d8ea12c6f4	fixed concatenation syntax	2022-07-05 22:36:54 +00:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
David Harris	8372bc86a7	Removing unused signals	2022-05-12 14:36:15 +00:00
David Harris	cb1a7d54a4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-05-03 08:53:35 -07:00
David Harris	4fbf78e049	clean up sram1p1rw; still doesn't work on Modelsim 2022.1	2022-05-03 08:31:54 -07:00
David Harris	7e3f75a35d	Formatting cache.sv	2022-05-03 10:53:20 +00:00
David Harris	bc132c3e20	sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera	2022-05-03 03:50:41 -07:00
David Harris	3f2ec0499f	Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.	2022-05-03 03:45:41 -07:00
Ross Thompson	ab9738d3be	Hacky fix to prevent ITLBMissF and TrapM bug.	2022-04-12 17:56:23 -05:00
Ross Thompson	b2a77da96b	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
Ross Thompson	3dbf6790e1	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	81a2fbb6d2	mild cleanup.	2022-03-11 13:05:47 -06:00
Ross Thompson	11e5aad38a	Moved subcachelineread inside the cache. There is some ugliness to still resolve.	2022-03-11 12:44:04 -06:00
Ross Thompson	a12016e69b	Moved subcacheline read inside the cache.	2022-03-11 11:03:36 -06:00
Ross Thompson	326ecda060	removed unused parameter.	2022-03-11 10:43:54 -06:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00