Quswar Abid
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7b441d2881
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Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV
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2024-04-23 18:20:29 -07:00 |
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Kunlin Han
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9be0303493
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Add support for dumping vcd.
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2024-04-22 13:03:51 -07:00 |
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Kunlin Han
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c134b712c4
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Merge branch 'main' into verilator
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2024-04-22 11:35:18 -07:00 |
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Kunlin Han
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c383bef1ad
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Run verilator configurations and testsuites in different folders.
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2024-04-22 11:32:46 -07:00 |
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slmnemo
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6458fa5642
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Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
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2024-04-20 14:46:35 -07:00 |
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David Harris
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84e8d86d2a
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Merge pull request #739 from Karl-Han/deriv_support
Add extra path to search for deriv/buildroot
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2024-04-20 11:23:54 -07:00 |
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slmnemo
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2b0cf90a99
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Merged with merge conflict
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2024-04-17 10:47:28 -07:00 |
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Kunlin Han
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91a88fa46c
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Update sim/verilator/Makefile with more comments and merging variables.
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2024-04-17 09:52:54 -07:00 |
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Kunlin Han
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392eedb342
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Update sim/verilator/Makefile with constants for simplicity.
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2024-04-16 18:54:11 -07:00 |
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Kunlin Han
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6f6b1fd1fd
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Add extra path to search for deriv/buildroot.
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2024-04-16 18:45:21 -07:00 |
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slmnemo
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554f818a8c
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Fixed wave.do to match new conditional generate block names
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2024-04-16 14:43:38 -07:00 |
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Rose Thompson
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dd3460c1a9
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Fixed makefile and regression-wally so that code coverage now works.
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2024-04-16 15:44:42 -05:00 |
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Rose Thompson
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1eb1beed95
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Fixed merge conflict bug in the last pull request.
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2024-04-16 10:32:24 -05:00 |
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Rose Thompson
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9fe86712d8
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Merge branch 'main' into wsim_verilator
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2024-04-16 09:07:50 -05:00 |
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David Harris
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160162c98a
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Merge pull request #728 from Karl-Han/verilator_getenv
Add support for getenvval as wrapper for Verilator's getenv
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2024-04-15 17:55:34 -06:00 |
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slmnemo
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4b80457f3e
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Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
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2024-04-12 21:58:20 -07:00 |
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Kunlin Han
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7b5972ea82
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Merge branch 'verilator_getenv' into wsim_verilator
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2024-04-12 15:27:09 -07:00 |
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Kunlin Han
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4d9de94029
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Add support for getenvval as wrapper for Verilator's getenv.
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2024-04-12 14:59:04 -07:00 |
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Kunlin Han
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a55bb01d1d
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Update README and put logs in the right places.
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2024-04-11 20:16:55 -07:00 |
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Kunlin Han
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e25177cf4c
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Add verilator support for wsim.
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2024-04-11 20:02:20 -07:00 |
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slmnemo
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90040a6a21
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Added extra path to run-imperas-linux.sh to match new questa directory with .do files
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2024-04-09 16:13:31 -07:00 |
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Rose Thompson
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bb072fba84
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Fixed the buildroot issue.
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2024-04-06 18:25:53 -05:00 |
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Rose Thompson
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d0d1166e3f
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Got the separation of the -G and +variable arguments in the questa do file.
regression still runs.
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2024-04-06 18:04:48 -05:00 |
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Rose Thompson
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cdcff9d368
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Updated sim-wally to work with new run scripts.
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2024-04-06 16:32:07 -05:00 |
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Rose Thompson
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46fdfde7ec
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Removed unnecessary display from testbench.
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2024-04-06 16:10:18 -05:00 |
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David Harris
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c73a48cf22
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Removed unused wave-dos
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2024-04-06 13:52:13 -07:00 |
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David Harris
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e8111da88a
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Removed unused old regression-wally
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2024-04-06 13:47:44 -07:00 |
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David Harris
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6b844a2e6e
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Added GUI support and removed unused wave files
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2024-04-06 13:43:06 -07:00 |
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David Harris
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3c855e3e90
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Passing arguments to buildroot, not yet checking result correctly
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2024-04-06 11:42:41 -07:00 |
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David Harris
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ac9a21873d
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Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
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2024-04-06 10:34:21 -07:00 |
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David Harris
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347df26713
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Fixed regression running; buildroot pending
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2024-04-06 09:46:56 -07:00 |
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David Harris
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9ee7544d3c
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TestFloat running; normal testbench broken
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2024-04-06 09:28:07 -07:00 |
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David Harris
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4b19f6d542
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testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./
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2024-04-06 08:22:39 -07:00 |
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David Harris
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4cc9dd7583
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regression-wally refactoring to support mulitple simulators
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2024-04-05 21:45:56 -07:00 |
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David Harris
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7b56809323
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wsim runs a Questa sim
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2024-04-05 19:08:14 -07:00 |
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David Harris
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a1d3e5b15e
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Moved do files into questa
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2024-04-05 18:42:48 -07:00 |
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David Harris
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a8a03d6011
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Reorganizing sim directory for multiple simulators
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2024-04-05 18:19:46 -07:00 |
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slmnemo
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3ee25c8936
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Merged testbench changes
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2024-04-05 17:20:03 -07:00 |
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slmnemo
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5378b61eb2
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Added UART output file buildroot_uart.out for Linux test 'buildroot'.
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2024-04-05 17:18:03 -07:00 |
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David Harris
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ccd0e9cd0c
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Clean up testbench-fp for Verilator
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2024-04-03 17:26:41 -07:00 |
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David Harris
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ae8d581f4e
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Started implementing Verilator for testfloat
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2024-04-03 17:09:19 -07:00 |
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Divya2030
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135f3b6f8f
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vcs testbench
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2024-04-03 10:39:02 -07:00 |
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Ross Thompson
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101021222b
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Merge branch 'main' of github.com:ross144/cvw into main
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2024-03-29 14:39:39 -05:00 |
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Ross Thompson
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33a26fb78c
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Updates to branch predictor collection.
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2024-03-29 13:52:28 -05:00 |
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Quswar Abid
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21dd4649de
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ISACOV is functioning - March 27, 2024
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2024-03-26 14:17:41 -07:00 |
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slmnemo
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6fbac9ec97
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Merge branch 'main' of https://github.com/openhwgroup/cvw into nightly-regression
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2024-03-26 10:29:00 -07:00 |
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slmnemo
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efb68e7eeb
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Added dumptvs function to Linux makefile to create linux-testvectors in /opt/riscv directory
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2024-03-26 10:28:50 -07:00 |
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David Harris
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f0b29d3083
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AMO max/min comparator optimization
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2024-03-24 17:05:32 -07:00 |
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Kevin Kim
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c8b84ebbc5
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regression-wally -softfloat with updated derived configs
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2024-03-20 09:58:14 -07:00 |
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Kevin Kim
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ccf2c270a1
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Merge branch 'update_derived_configs' of https://github.com/kevindkim723/cvw into update_derived_configs
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2024-03-20 09:54:08 -07:00 |
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