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78e513160e
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88 Commits

Author SHA1 Message Date
bbracker
78e513160e put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests 2021-07-19 16:19:24 -04:00
bbracker
76be84fa92 whoops MTIMECMP is always 64 bits 2021-07-19 15:40:53 -04:00
bbracker
77b690faf0 make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
David Harris
bbbc1d2f89 Simplified PLIC with generate 2021-07-04 19:17:15 -04:00
David Harris
ce3edd0288 Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 19:02:56 -04:00
David Harris
57e1111df3 Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
bbracker
96939328ea for GPIO give priority to clearing interrupts 2021-07-04 17:20:16 -04:00
David Harris
b5df9b282d Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
David Harris
c016ab8e58 Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
David Harris
ee605d7550 Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker 2021-07-03 03:29:33 -04:00
Kip Macsai-Goren
1485d29dde Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
David Harris
1972d83002 Refactored pmachecker to have adrdecs used in uncore 2021-06-23 01:41:00 -04:00
bbracker
b43a8885cd give EBU a dedicated PMA unit as just an address decoder 2021-06-22 18:28:08 -04:00
David Harris
0a59b006ab Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals 2021-06-20 22:59:04 -04:00
David Harris
72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
7d1469a06c provide time and timeh CSRs based on CLINT's counter 2021-06-17 08:38:30 -04:00
bbracker
7a652139b5 mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
Ross Thompson
5d7ca87982 fixed the mtime register. 2021-06-11 13:50:13 -05:00
David Harris
0e4e091a39 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-10 10:47:55 -04:00
David Harris
c3d106f0f0 Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
bbracker
9c3cb0d2bf peripheral lint fixes 2021-06-10 10:19:10 -04:00
bbracker
f0266f621b merge 2021-06-10 10:03:01 -04:00
bbracker
58d0e46d02 UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
cfe5c27946 Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
bbracker
8338b3bd34 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
8554f2f3cd plic implementation optimizations 2021-05-19 18:10:48 +00:00
David Harris
96e90402c5 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
062120f944 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
David Harris
743011194b Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
8758b6efa1 Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
David Harris
1f2da4c457 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
bbracker
9c08ce5359 rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
bbracker
c796547156 greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
bbracker
80a67dc906 declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
eca92041e9 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
8f4da826fb plic subword access compliance 2021-04-04 23:10:33 -04:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
bbracker
d52c71086a added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00