cvw/wally-pipelined/src/uncore
Ross Thompson 7f12c7af90 Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.

instr
addr   correct   got
2021-04-07 19:12:43 -05:00
..
adrdec.sv busybear: fix bootram range 2021-03-01 17:45:21 +00:00
clint.sv clint HREADY signal update 2021-03-12 20:23:55 -05:00
dtim.sv Switch to use RV64IC for the benchmarks. 2021-04-07 19:12:43 -05:00
gpio.sv upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
imem.sv Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
plic.sv first pass at PLIC interface 2021-03-22 10:14:21 -04:00
subwordwrite.sv Data memory bus integration 2021-02-07 23:21:55 -05:00
uart.sv added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
uartPC16550D.sv first merge of ahb fix 2021-03-05 14:24:22 -05:00
uncore.sv first pass at PLIC interface 2021-03-22 10:14:21 -04:00