Thomas Fleming
d281ecd067
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
bbracker
ccff1e6c99
rv64 interrupt servicing
2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1
busybear: use (slightly) less terrible verilog
2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d
busybear testbench updates
...
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic
I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
bbracker
0c85b1c201
integrated peripheral testing into existing workflow
2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8
merge testbench
2021-04-08 14:28:01 -04:00
Noah Boorstin
5f1cd43033
try to remove git-lfs stuff
2021-04-08 13:23:11 -04:00
Domenico Ottolia
1bdfac6a77
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771
Implement support for superpages
2021-04-08 02:44:59 -04:00
Domenico Ottolia
9b82fbff5a
Add privileged tests to testbench
2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467
Add passing mtval and mepc tests
2021-04-07 02:21:05 -04:00
Noah Boorstin
c820910b29
add busybear boot files with git-lfs
2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04
busybear: reenable 'ruthless' CSR checking
2021-04-05 12:53:30 -04:00
bbracker
ce7b2314ef
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
8f31e00f6a
Merge branch 'mmu' into main
...
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9
busybear: temporary stop after 800k instrs
2021-04-03 21:37:57 -04:00
Katherine Parry
08b31f7b2a
Integrated FPU
2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65
Put back imperas testbench until figure out why m_supported is running for rv64ic
2021-04-02 08:19:25 -05:00
James E. Stine
9026357350
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
Thomas Fleming
06032936bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d
Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu
2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Noah Boorstin
4e62c7d5f5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7
busybear: clean up questa warnings
2021-03-31 14:02:15 -04:00
Thomas Fleming
e3d548d452
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3
Update virtual memory tests and move to separate folder
2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7
Add one more test to WALLY-CAUSE, and update privileged testgen
2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58
Add mcause tests to testbench
2021-03-30 17:17:59 -04:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Domenico Ottolia
fb00d0f209
Fix bugs with privileged tests
2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Teo Ene
1e691e120b
Fix typo from last commit
2021-03-24 17:09:58 -05:00
Teo Ene
6a7b69ff2d
Updated coremark_bare testbench for IM
2021-03-24 17:04:43 -05:00
Domenico Ottolia
3909158619
re-organize privileged tests to be in rv64p to rv32p folders
2021-03-24 13:51:25 -04:00
Noah Boorstin
43d23e3d9b
busybear: add better warning on illegal instruction
...
...also it seems that mret is being picked up as an illegal instruction??
2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0
busybear: temporarially force rf[5] correct after failure to read CSR
2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0
busybear: finally get the right error
2021-03-22 16:52:22 -04:00
Noah Boorstin
7350b9f18f
busybear: comment out some debug printing
2021-03-22 14:54:05 -04:00
Noah Boorstin
c4fb51fad1
regression: expect 200k instead of 100k busybear instrs
...
and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
Shreya Sanghai
804407eab7
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Teo Ene
0ff785549e
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed
adapted coremark bare testbench to new dtim RAM HDL
2021-03-17 16:59:02 -05:00
Teo Ene
29634f1475
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
90946d61c5
fix to last commit
2021-03-17 15:02:15 -05:00
Teo Ene
ca901513c8
Added Ross's addr lab stuff to coremark stuff
2021-03-17 14:50:54 -05:00
