Ross Thompson
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754f55c564
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Updated the .gitignore to reject all the extra compiled objects for the branchmarks.
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2021-03-24 10:30:19 -05:00 |
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Ross Thompson
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58487db60a
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Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
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2021-03-24 09:22:21 -05:00 |
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Ross Thompson
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ace39940b4
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Fixed RAS errors. Still some room for improvement with the BTB and RAS.
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2021-03-23 23:00:44 -05:00 |
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Ross Thompson
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72d25d4443
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Fixed a bunch of bugs with the RAS.
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2021-03-23 21:49:16 -05:00 |
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Ross Thompson
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c318606f05
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Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
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2021-03-23 20:20:23 -05:00 |
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Ross Thompson
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9d5c351340
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fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
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2021-03-23 20:06:45 -05:00 |
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Ross Thompson
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dee5d16850
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fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
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2021-03-23 16:53:48 -05:00 |
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Ross Thompson
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4836e8fe2c
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Simulation definitely shows the branch predictor counters and branch predictor don't work. :(
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2021-03-23 14:04:58 -05:00 |
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Ross Thompson
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c7e34bd4a0
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added a whole bunch of interseting test code for branches which does not work.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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c4f7c65210
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updated the branch predictor config.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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9909bdd4d5
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Added first benchmark.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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cebb2bc44d
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Temporary exe2memfile0.pl script to support starting addresses of 0.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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e6aef66853
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Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
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2021-03-23 13:54:59 -05:00 |
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Shreya Sanghai
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09b90557f7
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PC counts branch instructions
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2021-03-23 14:25:51 -04:00 |
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Jarred Allen
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789c189260
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Another tweak to regression-wally.py comments
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2021-03-23 00:18:38 -04:00 |
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Jarred Allen
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2c4eda2ba3
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Slight change to regression-wally.py comments
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2021-03-23 00:02:40 -04:00 |
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Noah Boorstin
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43d23e3d9b
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busybear: add better warning on illegal instruction
...also it seems that mret is being picked up as an illegal instruction??
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2021-03-22 18:24:35 -04:00 |
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Noah Boorstin
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4160bf50b0
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busybear: temporarially force rf[5] correct after failure to read CSR
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2021-03-22 18:12:41 -04:00 |
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Noah Boorstin
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4be19421c4
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busybear: allow overwriting read values
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2021-03-22 17:28:44 -04:00 |
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Noah Boorstin
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b4166e9fd0
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busybear: finally get the right error
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2021-03-22 16:52:22 -04:00 |
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bbracker
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c3a6d6bf42
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added delays to uart AHB signals
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2021-03-22 15:40:29 -04:00 |
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Noah Boorstin
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7350b9f18f
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busybear: comment out some debug printing
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2021-03-22 14:54:05 -04:00 |
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Noah Boorstin
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c4fb51fad1
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regression: expect 200k instead of 100k busybear instrs
and a minor busybear bugfix
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2021-03-22 14:47:52 -04:00 |
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bbracker
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eea7e2e47e
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Katherine Parry
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9af0ad815c
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fixed various bugs in the FMA
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2021-03-21 22:53:04 +00:00 |
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Katherine Parry
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fd381e60d7
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messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic
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2021-03-20 02:05:16 +00:00 |
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bbracker
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df51d9908d
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AHB bugfixes and sim waveview refactoring
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2021-03-18 18:25:12 -04:00 |
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Shreya Sanghai
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804407eab7
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fixed minor bugs in testbench
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2021-03-18 17:37:10 -04:00 |
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Shreya Sanghai
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dfc86539cc
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Ross Thompson
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9386e6a524
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Switched to gshare from global history.
Fixed a few minor bugs.
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2021-03-18 16:05:59 -05:00 |
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Ross Thompson
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181a28e875
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Fixed minor bug with the size of gshare.
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2021-03-18 16:00:09 -05:00 |
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Shreya Sanghai
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f35d3b39c8
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removed unnecesary PC registers in ifu
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2021-03-18 16:31:21 -04:00 |
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Thomas Fleming
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859d242d81
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-18 14:36:42 -04:00 |
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Thomas Fleming
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062c4d40da
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Connect tlb, pagetablewalker, and memory
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2021-03-18 14:35:46 -04:00 |
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Thomas Fleming
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f04e554e35
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Improve page table creation in python file
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2021-03-18 14:27:09 -04:00 |
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Noah Boorstin
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847bf0b9a6
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Noah Boorstin
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fa1407f6e3
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everyone gets a bootram
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2021-03-18 12:35:37 -04:00 |
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Noah Boorstin
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a226e24ed3
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busybear: update memory map, add GPIO
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2021-03-18 12:17:35 -04:00 |
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Teo Ene
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0ff785549e
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Switched coremark to RV64IM
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2021-03-17 22:39:56 -05:00 |
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Teo Ene
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db164462ed
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adapted coremark bare testbench to new dtim RAM HDL
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2021-03-17 16:59:02 -05:00 |
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Teo Ene
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29634f1475
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Temporarily reverted my last few commits
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2021-03-17 15:16:01 -05:00 |
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Teo Ene
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e6661ea26a
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fix to last commit
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2021-03-17 15:07:02 -05:00 |
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Teo Ene
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90946d61c5
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fix to last commit
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2021-03-17 15:02:15 -05:00 |
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Teo Ene
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083a24c06b
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addition to last commit
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2021-03-17 14:52:31 -05:00 |
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Teo Ene
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ca901513c8
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Added Ross's addr lab stuff to coremark stuff
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2021-03-17 14:50:54 -05:00 |
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Elizabeth Hedenberg
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bccd37d778
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fixing coremark branch prediction
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2021-03-17 15:15:55 -04:00 |
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Elizabeth Hedenberg
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74ebe0bef2
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replicating coremark changes into coremark bare
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2021-03-17 14:36:34 -04:00 |
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Elizabeth Hedenberg
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a3b2ffb2c9
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Merge branch '3_3_2021' into main
Making sure coremark works with spring break changes
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2021-03-17 14:11:37 -04:00 |
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Ross Thompson
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7bc95ba073
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Fixed issue with sim-wally-batch. Are people still using this script?
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2021-03-17 11:17:52 -05:00 |
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Ross Thompson
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0e2352a6de
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-17 11:07:57 -05:00 |
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