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Configurable RISC-V Processor
418 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
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Ross Thompson 58487db60a Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
2021-03-24 09:22:21 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack. 2021-03-24 09:22:21 -05:00
wally-pipelined Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
.gitignore Added debug option to disable the function radix if not needed. 2021-03-10 15:17:02 -06:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor