Ross Thompson
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d83db2cde5
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Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
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2022-04-04 09:57:26 -05:00 |
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Ross Thompson
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fd9a33e453
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-03 17:56:55 -05:00 |
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Ross Thompson
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e7abcd862f
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fpga simulation works again.
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2022-04-03 17:31:07 -05:00 |
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Ross Thompson
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88290a4bad
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-03 17:30:47 -05:00 |
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David Harris
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6966554ee8
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Fixed bug with CSRRS/CSRRC for MIP/SIP
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2022-04-03 20:18:25 +00:00 |
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Ross Thompson
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d135866098
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-02 16:39:54 -05:00 |
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Ross Thompson
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5ef6cde52e
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Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
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Ross Thompson
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aaf6ea8d8d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-02 16:35:59 -05:00 |
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Kip Macsai-Goren
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c40ddc4afb
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small bug fixes to 64 bit library
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2022-04-02 19:17:34 +00:00 |
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Kip Macsai-Goren
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64afc99a02
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added unfinished tests to 32 bit library
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2022-04-02 19:15:07 +00:00 |
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Kip Macsai-Goren
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39c1fdb024
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updated 32 bit tests to be in line with 64 bit test library
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2022-04-02 19:14:12 +00:00 |
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Kip Macsai-Goren
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f7bbae8746
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removed compressed instructions from privileged tests
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2022-04-02 19:12:44 +00:00 |
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Kip Macsai-Goren
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cdea062287
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added RV64IA config to have a config without compressed instructions
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2022-04-02 18:24:08 +00:00 |
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Ross Thompson
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987236e463
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 17:18:25 -05:00 |
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Ross Thompson
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57eba4355e
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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Ross Thompson
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f58a1eff9e
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Fixed linting issues.
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2022-04-01 15:20:45 -05:00 |
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Ross Thompson
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178ecaa451
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 12:50:34 -05:00 |
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Ross Thompson
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0340c0fd44
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Added wave config
added new signals to ILA.
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2022-04-01 12:44:14 -05:00 |
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David Harris
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97de3dfc21
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-04-01 16:49:18 +00:00 |
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David Harris
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4f7c37e406
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Changed Linux disassembly to -S to preserve source code lines
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2022-04-01 16:49:13 +00:00 |
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bbracker
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cbff9a7755
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expand WALLY-PERIPH test to use SEIP on PLIC context 1
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2022-03-31 18:02:06 -07:00 |
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bbracker
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36c30b14c1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 17:54:43 -07:00 |
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bbracker
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e60139d3ee
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fix lingering overrun error bug
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2022-03-31 17:54:32 -07:00 |
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Ross Thompson
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cb945a6a6a
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Added PLIC to ILA.
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2022-03-31 16:44:49 -05:00 |
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Ross Thompson
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1586f893b1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 16:30:55 -05:00 |
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Ross Thompson
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7e05935348
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 15:50:04 -05:00 |
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Ross Thompson
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e81f317764
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Notes on what to change in ram.sv.
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2022-03-31 15:48:15 -05:00 |
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bbracker
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d32e1147bf
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 13:46:32 -07:00 |
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bbracker
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34c94f150e
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simplify plic logic
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2022-03-31 13:46:24 -07:00 |
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David Harris
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2ed1c9f14f
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Added SystemVerilog flag to fma.do so that fma16 compiles properly
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2022-03-31 17:00:38 +00:00 |
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Ross Thompson
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fb0eec0f76
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:39:41 -05:00 |
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Ross Thompson
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0942429b7f
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Forced to go back to hard coded preload.
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2022-03-31 11:39:37 -05:00 |
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Ross Thompson
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a6d090a7c0
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:38:55 -05:00 |
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Ross Thompson
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dc48d84dd6
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Modified clint to support all byte write sizes.
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2022-03-31 11:31:52 -05:00 |
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David Harris
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93d6b2fb62
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Added synthesis script for fma16
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2022-03-31 00:51:33 +00:00 |
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David Harris
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f917ed7ed0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 23:06:36 +00:00 |
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Ross Thompson
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4f1258043d
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Updated constraints file.
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2022-03-30 17:48:44 -05:00 |
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Ross Thompson
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9f9a273d2c
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Added bootrom.txt.
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2022-03-30 17:29:48 -05:00 |
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Ross Thompson
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07eba7df45
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 17:28:30 -05:00 |
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bbracker
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54b9745a75
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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b2a77da96b
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Changed sram1p1rw to have the same type of bytewrite enables as bram.
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2022-03-30 11:38:25 -05:00 |
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David Harris
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44f94173bf
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 16:26:27 +00:00 |
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David Harris
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1f10a96aa2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 16:13:42 +00:00 |
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Ross Thompson
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3ac736e2d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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370a075fa1
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Partial cleanup of memories.
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2022-03-30 11:09:21 -05:00 |
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Ross Thompson
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1993069986
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Kip Macsai-Goren
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b252122d62
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fixed arch bge test signature output location after update
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2022-03-29 20:45:18 +00:00 |
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David Harris
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057ee56d7e
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Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv
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2022-03-29 19:16:41 +00:00 |
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