David Harris
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f12cdf55fe
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-06-27 03:22:55 -07:00 |
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David Harris
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2845d7eab1
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Merge pull request #856 from jordancarlin/testbench_cleanup
Testbench cleanup
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2024-06-27 03:21:53 -07:00 |
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Jordan Carlin
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784151e165
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Fix testbench_fp to use F_SUPPORTED, not S_SUPPORTED
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2024-06-26 22:29:00 -07:00 |
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Jordan Carlin
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032de34dbd
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Lint fixes for no priv mode configs
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2024-06-26 22:15:18 -07:00 |
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Jordan Carlin
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47e67e99ff
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Add no priv mode tests to regression
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2024-06-26 22:00:29 -07:00 |
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Jordan Carlin
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c3cb4e5d1c
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Fix FPU without S_SUPPORTED - #840
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2024-06-26 22:00:29 -07:00 |
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Jordan Carlin
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607a09ca62
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Add derived configs without privilege modes
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2024-06-26 21:59:53 -07:00 |
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Jordan Carlin
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d3bb39d918
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Fix derived configs with D_SUPPORTED = 0
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2024-06-26 21:25:59 -07:00 |
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Jordan Carlin
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221f710baf
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Use QUESTA as flag for
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2024-06-26 21:18:40 -07:00 |
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Ross Thompson
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ccf4bb8ddc
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Maybe have the incircuit trigger working.
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2024-06-26 16:15:46 -07:00 |
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David Harris
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8fe2052b1f
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Fix derived configuration with new derivgen script
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2024-06-26 16:09:59 -07:00 |
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David Harris
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21e5fa3103
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Merge pull request #854 from Shreesh-Kulkarni/main
Files for Quad Precision Testing Support for Wally
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2024-06-26 11:41:26 -07:00 |
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Shreesh-Kulkarni
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93fb0f2a84
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Files for Quad Precision Testing Support for Wally
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2024-06-26 11:36:04 -07:00 |
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Ross Thompson
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612a281f62
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Added module to receive ethernet frame and trigger the ila.
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2024-06-26 11:05:31 -07:00 |
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David Harris
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a013c7083f
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Merge pull request #853 from jordancarlin/derivgen_fix
Fix derivgen
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2024-06-26 08:31:22 -07:00 |
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Jordan Carlin
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1a1da9b2c4
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Update derivlist.txt based on exact matching
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2024-06-26 07:49:27 -07:00 |
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Jordan Carlin
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0da6e35988
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Fix derivgen.pl to find exact keys
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2024-06-26 07:45:04 -07:00 |
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Jordan Carlin
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f003f8fae9
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Merge pull request #852 from davidharrishmc/dev
Clean up unused signals for derived configurations
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2024-06-26 07:34:00 -07:00 |
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David Harris
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0fcc7878dc
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Updated march lists
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2024-06-25 21:54:58 -07:00 |
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Ross Thompson
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74189e1e4b
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Have vivado triggering the ILA after the mismatch but the latency is way too long.
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2024-06-25 17:04:14 -07:00 |
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Ross Thompson
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fa26c9a8b5
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Added pipe to vivado to create ila trigger from rvvidaemon.
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2024-06-25 13:07:46 -07:00 |
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Kevin Kim
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eeea783da0
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lint
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2024-06-21 23:15:34 -07:00 |
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Kevin Kim
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4877633977
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lint fixes tests vh
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2024-06-21 22:16:09 -07:00 |
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Kevin Kim
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19f0cf7a35
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putting back tests in tests vh
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2024-06-21 21:51:44 -07:00 |
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Kevin Kim
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e6dc50308a
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integer postprocessing hardware matches diagram
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2024-06-21 21:50:55 -07:00 |
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Kevin Kim
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00bf3faa9c
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changed intdivb width
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2024-06-21 21:31:19 -07:00 |
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Jordan Carlin
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b76941d278
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Use VCS built-in default macro instead of defining SIM_VCS
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2024-06-21 15:17:59 -07:00 |
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Kevin Kim
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9a59c8e07f
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reduced bit widths for integer on fpu
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2024-06-20 23:46:45 -07:00 |
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Ross Thompson
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249d58244a
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It's working!!!!!!
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2024-06-20 15:48:30 -07:00 |
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Ross Thompson
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1c6ebb86a3
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Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
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2024-06-20 12:54:12 -07:00 |
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Rose Thompson
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e1fc44a5bf
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Merge pull request #849 from davidharrishmc/dev
lint cleanup and divider optimization
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2024-06-20 09:04:19 -07:00 |
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David Harris
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486e6ff0f6
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-06-20 08:43:48 -07:00 |
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David Harris
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d8d94eeafa
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Merge pull request #808 from jordancarlin/main
Update riscv-arch-test
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2024-06-20 08:43:41 -07:00 |
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Jordan Carlin
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90f5a4ef48
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Only run fmsub_b15 for f_fma test
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2024-06-20 07:48:33 -07:00 |
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David Harris
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25780f53ce
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Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.
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2024-06-20 00:57:58 -07:00 |
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David Harris
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27457f4ef4
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Merge pull request #848 from ross144/main
Covergen doesn't produce stores and riscv-dv only generates tests
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2024-06-20 00:10:33 -07:00 |
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David Harris
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0ab3f28991
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Lint cleanup
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2024-06-20 00:10:03 -07:00 |
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Ross Thompson
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e88a2f7eaa
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Merge branch 'main' of github.com:ross144/cvw into main
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2024-06-19 15:14:28 -07:00 |
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Ross Thompson
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9e93f21990
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Updated covergen to not include stores as they are incomplete.
Modified makefile riscv-dv to not simulation only generate tests.
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2024-06-19 15:13:49 -07:00 |
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David Harris
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5f1ee1ac85
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Fixed undriven signal in certain config
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2024-06-19 15:12:35 -07:00 |
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David Harris
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e4febf25ae
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Merge pull request #847 from ross144/main
Partial fix for verilator +args. At least compiles.
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2024-06-19 14:27:39 -07:00 |
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Rose Thompson
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46ace521c6
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Updated verilator makefile.
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2024-06-19 16:25:31 -05:00 |
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David Harris
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9922b24cbe
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-06-19 14:13:08 -07:00 |
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David Harris
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1ffd30f2e1
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Merge pull request #846 from ross144/main
Removes *** from all system verilog
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2024-06-19 14:12:56 -07:00 |
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Ross Thompson
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685f4d3807
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Removed the last of the ***.
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2024-06-19 14:00:31 -07:00 |
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Ross Thompson
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2d8973df1d
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Updated wavefile to use new names.
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2024-06-19 13:57:28 -07:00 |
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Ross Thompson
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64712d2243
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Updated wave to match changes in testbench.
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2024-06-19 13:51:50 -07:00 |
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Ross Thompson
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d368f2e77e
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Removed *** from testbench.
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2024-06-19 13:51:37 -07:00 |
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Ross Thompson
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7f0ba87231
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Updated comments in uart.
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2024-06-19 13:51:30 -07:00 |
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Ross Thompson
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91c844ca45
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Removed more *** from camline and csrc.
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2024-06-19 12:31:50 -07:00 |
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