Commit Graph

9012 Commits

Author SHA1 Message Date
David Harris
f12cdf55fe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-06-27 03:22:55 -07:00
David Harris
2845d7eab1
Merge pull request #856 from jordancarlin/testbench_cleanup
Testbench cleanup
2024-06-27 03:21:53 -07:00
Jordan Carlin
784151e165
Fix testbench_fp to use F_SUPPORTED, not S_SUPPORTED 2024-06-26 22:29:00 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs 2024-06-26 22:15:18 -07:00
Jordan Carlin
47e67e99ff
Add no priv mode tests to regression 2024-06-26 22:00:29 -07:00
Jordan Carlin
c3cb4e5d1c
Fix FPU without S_SUPPORTED - #840 2024-06-26 22:00:29 -07:00
Jordan Carlin
607a09ca62
Add derived configs without privilege modes 2024-06-26 21:59:53 -07:00
Jordan Carlin
d3bb39d918
Fix derived configs with D_SUPPORTED = 0 2024-06-26 21:25:59 -07:00
Jordan Carlin
221f710baf
Use QUESTA as flag for 2024-06-26 21:18:40 -07:00
Ross Thompson
ccf4bb8ddc Maybe have the incircuit trigger working. 2024-06-26 16:15:46 -07:00
David Harris
8fe2052b1f Fix derived configuration with new derivgen script 2024-06-26 16:09:59 -07:00
David Harris
21e5fa3103
Merge pull request #854 from Shreesh-Kulkarni/main
Files for Quad Precision Testing Support for Wally
2024-06-26 11:41:26 -07:00
Shreesh-Kulkarni
93fb0f2a84 Files for Quad Precision Testing Support for Wally 2024-06-26 11:36:04 -07:00
Ross Thompson
612a281f62 Added module to receive ethernet frame and trigger the ila. 2024-06-26 11:05:31 -07:00
David Harris
a013c7083f
Merge pull request #853 from jordancarlin/derivgen_fix
Fix derivgen
2024-06-26 08:31:22 -07:00
Jordan Carlin
1a1da9b2c4
Update derivlist.txt based on exact matching 2024-06-26 07:49:27 -07:00
Jordan Carlin
0da6e35988
Fix derivgen.pl to find exact keys 2024-06-26 07:45:04 -07:00
Jordan Carlin
f003f8fae9
Merge pull request #852 from davidharrishmc/dev
Clean up unused signals for derived configurations
2024-06-26 07:34:00 -07:00
David Harris
0fcc7878dc Updated march lists 2024-06-25 21:54:58 -07:00
Ross Thompson
74189e1e4b Have vivado triggering the ILA after the mismatch but the latency is way too long. 2024-06-25 17:04:14 -07:00
Ross Thompson
fa26c9a8b5 Added pipe to vivado to create ila trigger from rvvidaemon. 2024-06-25 13:07:46 -07:00
Kevin Kim
eeea783da0 lint 2024-06-21 23:15:34 -07:00
Kevin Kim
4877633977 lint fixes tests vh 2024-06-21 22:16:09 -07:00
Kevin Kim
19f0cf7a35 putting back tests in tests vh 2024-06-21 21:51:44 -07:00
Kevin Kim
e6dc50308a integer postprocessing hardware matches diagram 2024-06-21 21:50:55 -07:00
Kevin Kim
00bf3faa9c changed intdivb width 2024-06-21 21:31:19 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS 2024-06-21 15:17:59 -07:00
Kevin Kim
9a59c8e07f reduced bit widths for integer on fpu 2024-06-20 23:46:45 -07:00
Ross Thompson
249d58244a It's working!!!!!! 2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3 Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
Removed the external reset of the phy and now it always reliably starts in the same way.  The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Rose Thompson
e1fc44a5bf
Merge pull request #849 from davidharrishmc/dev
lint cleanup and divider optimization
2024-06-20 09:04:19 -07:00
David Harris
486e6ff0f6 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-06-20 08:43:48 -07:00
David Harris
d8d94eeafa
Merge pull request #808 from jordancarlin/main
Update riscv-arch-test
2024-06-20 08:43:41 -07:00
Jordan Carlin
90f5a4ef48
Only run fmsub_b15 for f_fma test 2024-06-20 07:48:33 -07:00
David Harris
25780f53ce Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now. 2024-06-20 00:57:58 -07:00
David Harris
27457f4ef4
Merge pull request #848 from ross144/main
Covergen doesn't produce stores and riscv-dv only generates tests
2024-06-20 00:10:33 -07:00
David Harris
0ab3f28991 Lint cleanup 2024-06-20 00:10:03 -07:00
Ross Thompson
e88a2f7eaa Merge branch 'main' of github.com:ross144/cvw into main 2024-06-19 15:14:28 -07:00
Ross Thompson
9e93f21990 Updated covergen to not include stores as they are incomplete.
Modified makefile riscv-dv to not simulation only generate tests.
2024-06-19 15:13:49 -07:00
David Harris
5f1ee1ac85 Fixed undriven signal in certain config 2024-06-19 15:12:35 -07:00
David Harris
e4febf25ae
Merge pull request #847 from ross144/main
Partial fix for verilator +args. At least compiles.
2024-06-19 14:27:39 -07:00
Rose Thompson
46ace521c6 Updated verilator makefile. 2024-06-19 16:25:31 -05:00
David Harris
9922b24cbe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-06-19 14:13:08 -07:00
David Harris
1ffd30f2e1
Merge pull request #846 from ross144/main
Removes *** from all system verilog
2024-06-19 14:12:56 -07:00
Ross Thompson
685f4d3807 Removed the last of the ***. 2024-06-19 14:00:31 -07:00
Ross Thompson
2d8973df1d Updated wavefile to use new names. 2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243 Updated wave to match changes in testbench. 2024-06-19 13:51:50 -07:00
Ross Thompson
d368f2e77e Removed *** from testbench. 2024-06-19 13:51:37 -07:00
Ross Thompson
7f0ba87231 Updated comments in uart. 2024-06-19 13:51:30 -07:00
Ross Thompson
91c844ca45 Removed more *** from camline and csrc. 2024-06-19 12:31:50 -07:00