Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
Rose Thompson
d9ef588324
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 10:01:33 -05:00
Jordan Carlin
5687e31c15
Merge pull request #888 from davidharrishmc/dev
2024-07-21 12:04:29 -07:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642
Updated verilog-ethernet to be compatible with wally.
2024-07-19 13:36:26 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
Rose Thompson
9c1779a2d5
Added some documenation about sparse-checkout for verilog-ethernet submodule.
2024-07-19 13:11:48 -05:00
Rose Thompson
e751fbe865
Merge pull request #887 from davidharrishmc/dev
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Fully decode decompressed instructions, including hints and illegal registers/immediates
2024-07-19 09:23:36 -05:00
David Harris
c64c12dc6c
Detect illegal compressed immediates, hints
2024-07-18 22:48:32 -07:00
David Harris
945722cd5b
Neatly formatted decompress.sv
2024-07-18 22:01:43 -07:00
David Harris
ebea314a6e
Modified decompressor to look for illegal x0 values and hints
2024-07-18 21:38:17 -07:00
Rose Thompson
79d0cb96c2
Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo.
2024-07-18 18:22:26 -05:00
David Harris
3b4726ea99
Check legal compressed nonzero destination registers, add c.nop decoding
2024-07-18 09:30:16 -07:00
David Harris
df063acf61
Refactored decompression to use simpler default illegal instruction
2024-07-18 08:26:58 -07:00
Rose Thompson
2fa7c49d5e
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-18 09:38:20 -05:00
David Harris
4d36072f09
Converted regression-wally to use argparse
2024-07-17 06:04:21 -07:00
Rose Thompson
4c638f4fc9
Merge pull request #884 from davidharrishmc/dev
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Attempt on functional coverage
2024-07-16 18:42:19 -05:00
Rose Thompson
19e9dc5ce0
Fixed wally.do to correctly log functional coverage.
2024-07-16 15:52:52 -05:00
David Harris
25f271064f
Fixed slli.uw bug reported by Lee Moore 16 July 2024
2024-07-16 09:28:05 -07:00
David Harris
d86ef9673d
More attempts at functional coverage
2024-07-15 15:34:44 -07:00
David Harris
ac05fa5553
Attempt at functional coverage; breaks code and functional coverage
2024-07-15 14:20:48 -07:00
David Harris
ff15671878
Ignore functional coverage outputs
2024-07-15 14:19:37 -07:00
David Harris
c3267e8fa4
Fixed .gitignore
2024-07-15 05:46:35 -07:00
David Harris
3ce92ab0a5
Ignoring more sim files
2024-07-15 05:34:50 -07:00
David Harris
467436e30c
Renamed --coverage to --ccov and moved UCDB files to questa/ucdb
2024-07-15 05:32:16 -07:00
David Harris
975c72c91d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-15 04:27:59 -07:00
David Harris
affe15191e
Fixed wsim running iterelf tests/coverage
2024-07-15 03:44:14 -07:00
David Harris
459eaaef6a
Initial effort to make testbench_fp compatible with Verilator without breaking Questa
2024-07-14 20:08:33 -07:00
David Harris
1b5e63ebe2
Fixed elf handling
2024-07-14 09:49:15 -07:00
Rose Thompson
276cb558f0
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
David Harris
779458f14a
Waive CBO failures in iterelf because ImperasDV does not handle them properly yet
2024-07-13 22:08:57 -07:00
David Harris
904a081218
allow wsim to take .elf in testsuite argument; print error if ELF not found
2024-07-13 21:59:26 -07:00
David Harris
26d4fbcc19
Switched ImperasDV to RV64GCK model to support crypto (issue #872 )
2024-07-13 21:42:14 -07:00
Rose Thompson
d5a6d93554
Merge pull request #879 from JacobPease/main
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main
2024-07-12 09:32:13 -05:00
Jacob Pease
7f72fb8583
Updated riscv,isa-extensions property with the correct syntax. Added riscv,cbom-block-size.
2024-07-12 09:28:54 -05:00
Jordan Carlin
a4967138b6
Merge pull request #875 from ross144/main
2024-07-11 18:05:14 -07:00
Rose Thompson
82bd9ca200
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-11 11:32:12 -05:00
Rose Thompson
8f52e4ae42
Merge pull request #878 from JacobPease/main
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Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.
2024-07-11 11:25:24 -05:00
Jacob Pease
1a2607c3d9
Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.
2024-07-11 10:53:18 -05:00
Ross Thompson
c72f0fd504
Added csr comparison.
2024-07-11 10:49:06 -05:00
Ross Thompson
abf9da01ab
code cleanup.
2024-07-11 10:41:34 -05:00
Ross Thompson
f0096f5a43
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11
Yay! the trigger is correctly working now!
2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8
Really close to having the trigger in module work.
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Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
Ross Thompson
6734685333
Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
2024-07-09 19:04:18 -05:00
Ross Thompson
e0a1f0e39f
Really close now.
2024-07-09 14:21:43 -05:00
