136 Commits

Author	SHA1	Message	Date
Jordan Carlin	e98330bcdf	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-15 19:10:51 -07:00
Jordan Carlin	d9d5fc0827	Refactor gitignore	2024-08-15 11:14:22 -07:00
Jordan Carlin	9a70480ef6	Update CacheSim scripts with new wsim and directory structure. Give simulator choice and switch default to verilator.	2024-08-09 21:50:18 -07:00
Jordan Carlin	3a4018fa3d	Add zsbl to makefile	2024-08-08 20:53:40 -07:00
Huda-10xe	0303314f4e	Adding RVVI Functional Coverage Support	2024-08-07 14:31:16 +05:00
Rose Thompson	7223b15134	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
Rose Thompson	9471dcd296	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.	2024-07-19 17:08:47 -05:00
David Harris	ff15671878	Ignore functional coverage outputs	2024-07-15 14:19:37 -07:00
David Harris	c3267e8fa4	Fixed .gitignore	2024-07-15 05:46:35 -07:00
David Harris	3ce92ab0a5	Ignoring more sim files	2024-07-15 05:34:50 -07:00
David Harris	02a7a1696b	git ignore	2024-07-05 21:35:10 -07:00
David Harris	f7797d6092	First version of iterelf running; removed directory support from wsim	2024-07-03 14:54:46 -07:00
David Harris	af75140bbc	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-05-21 00:50:15 -07:00
David Harris	506973c27a	Added gfmul example	2024-05-15 19:29:42 -07:00
Jordan Carlin	bf397f791f	Change all SUPPORTED type localparamters to one bit logic. Update configs for consistency.	2024-05-14 16:24:26 -07:00
David Harris	064b0a60bc	Name cleanups	2024-05-04 03:27:39 -07:00
David Harris	c3d5596291	Ignore functcov tests	2024-05-03 11:44:55 -07:00
David Harris	84b37cacfa	Ignore VCS junk output	2024-04-30 08:59:32 -07:00
David Harris	8f0c68373e	Verilator fulladder example improvmeents	2024-04-28 22:08:00 -07:00
David Harris	5d97858806	Moved functional coverage files to sim/questa and to tests/riscvdv	2024-04-24 11:46:38 -07:00
David Harris	e2894ed278	derived nobpred_rv32gc config for coremark test	2024-04-24 04:41:25 -07:00
David Harris	a722c7cd08	Ignoring vcd output	2024-04-23 10:19:53 -07:00
David Harris	45196a9959	ignore VCS junk files	2024-04-21 19:49:55 -07:00
Rose Thompson	a85f55d3c7	Merge branch 'main' into docker	2024-04-16 09:10:08 -05:00
Rose Thompson	9fe86712d8	Merge branch 'main' into wsim_verilator	2024-04-16 09:07:50 -05:00
Kunlin Han	2fd0a724f2	Remove buildroot and testvector to avoid duplicate files.	2024-04-15 10:30:14 -07:00
David Harris	58d3df0d16	Merge pull request #724 from ross144/main ... added fortran comiler to buildroot for spec benchmarks.	2024-04-15 10:18:49 -06:00
Kunlin Han	e25177cf4c	Add verilator support for wsim.	2024-04-11 20:02:20 -07:00
Rose Thompson	cf27ef1729	Updated .gitignore for branch prediction results.	2024-04-11 10:31:27 -05:00
Jordan Carlin	1e3b602cc6	Add files built from examples to gitignore	2024-04-08 12:14:32 -07:00
David Harris	f5602d8b55	Ignore coremark_results	2024-04-08 05:57:50 -07:00
David Harris	4cc9dd7583	regression-wally refactoring to support mulitple simulators	2024-04-05 21:45:56 -07:00
Kunlin Han	c71cafbea6	Add linux/buildroot to .gitignore to ignore the intermediate built for RISCV/buildroot	2024-03-08 12:58:08 -08:00
David Harris	d52d2d7983	Initial derivgen working	2024-01-29 11:22:34 -08:00
David Harris	17cbdb53df	Progress on Verilator simulation. Full adder compiles and runs. Wally builds.	2023-12-31 09:53:13 -08:00
Rose Thompson	93c356d50d	Added files to ignore file.	2023-11-26 17:31:23 -06:00
David Harris	1d234c05c9	disassembleBootTrace works on first 50M lines of boot	2023-11-22 22:17:01 -08:00
David Harris	423ae2bb76	Ignore benchmark results	2023-11-17 17:02:32 -08:00
Rose Thompson	540d8d930d	Cleanup. ... Linux makefile wally tracer. probably reduce some complexity here.	2023-11-13 14:04:43 -06:00
David Harris	680fb3f30b	Conditionally instantiate hardware in ifu	2023-10-30 20:55:00 -07:00
David Harris	905c5da7a9	Tested assembly language file for the pause example	2023-10-24 10:45:41 -07:00
David Harris	7c1606264a	Adjusted synthesis scripts to report on DESIGN even when a wrapper is used	2023-10-19 06:16:52 -07:00
Ross Thompson	7aecd72c35	Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.	2023-06-22 12:55:49 -05:00
David Harris	59e1a69e25	ignore example binaries	2023-05-29 23:24:48 -07:00
David Harris	71fe8a57c6	Ignore IF_vectors	2023-04-28 06:20:12 -07:00
Limnanthes Serafini	abf9da3c8b	Git issues, repushing	2023-03-29 04:10:47 -07:00
David Harris	121d1cea62	Added csrwrites.S test case for privileged tests	2023-03-23 10:55:32 -07:00
David Harris	31021265b8	Makefile improvements	2023-03-22 11:17:17 -07:00
David Harris	4a1592ccf8	Building infrastructure for coverage directed tests	2023-03-22 04:37:13 -07:00
David Harris	3fa570835a	Ignore more log files left from ImperasDV	2023-03-19 10:26:53 -07:00