cvw/wally-pipelined/regression
2021-07-19 12:32:35 -05:00
..
slack-notifier added slack notifier for long sims 2021-06-22 08:31:41 -04:00
wave-dos change memread testvectors to not left-shift bytes and half-words 2021-07-18 21:49:53 -04:00
regression-wally.py change buildroot expectations to match reality 2021-07-19 13:20:53 -04:00
run_sim.sh Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
sim-buildroot start to add buildroot testbench 2021-04-16 23:27:29 -04:00
sim-buildroot-batch start to add buildroot testbench 2021-04-16 23:27:29 -04:00
sim-busybear busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
sim-busybear-batch busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
sim-wally Added test configurations 2021-01-25 11:28:43 -05:00
sim-wally-batch Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
sim-wally-batch-muldiv Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
sim-wally-batch-rv32ic fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
sim-wally-batch-rv32icfd Fixed lint warning 2021-07-14 21:24:48 -04:00
sim-wally-batch-rv64icfd Update rv64icfd batch script 2021-05-18 16:01:53 -05:00
sim-wally-muldiv Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
sim-wally-rv32ic fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
sim-wally-rv32icfd Fixed lint warning 2021-07-14 21:24:48 -04:00
sim-wally-rv64icfd Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
udiv.c Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
wally-buildroot-batch.do whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
wally-buildroot.do whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
wally-busybear-batch.do hptw: minor cleanup 2021-07-17 13:40:12 -04:00
wally-busybear.do stop busybear from hanging 2021-07-02 17:22:09 -05:00
wally-coremark_bare.do moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
wally-pipelined-batch-muldiv.do moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
wally-pipelined-batch-rv32icfd.do Fixed lint warning 2021-07-14 21:24:48 -04:00
wally-pipelined-batch-rv64icfd.do fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
wally-pipelined-batch.do hptw: minor cleanup 2021-07-17 13:40:12 -04:00
wally-pipelined-muldiv.do moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
wally-pipelined-ross.do Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
wally-pipelined-rv32icfd.do Fixed lint warning 2021-07-14 21:24:48 -04:00
wally-pipelined-rv64icfd.do fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
wally-pipelined.do moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
wally-privileged.do moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
wave-all.do Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
wave.do Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. 2021-07-19 12:32:16 -05:00