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Author SHA1 Message Date
Ross Thompson
6dd5668d21 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-22 18:07:32 -06:00
cturek
bdb9e24a66 Almost done with Int division 2022-11-22 22:22:59 +00:00
cturek
78c2ce5649 Updated testbench/wave for fdivsqrt new start signals 2022-11-22 22:22:26 +00:00
Ross Thompson
279f5bc615 Cleanup cacheLRU. 2022-11-22 14:59:01 -06:00
Ross Thompson
e1dbe58632 File name change for cachereplacement policy to cacheLRU 2022-11-20 22:35:02 -06:00
Ross Thompson
4e926ba4cf Signal name changes for LRU. 2022-11-20 22:31:36 -06:00
Ross Thompson
e99a424ddc Updated top level fpga file. 2022-11-18 11:10:45 -06:00
Ross Thompson
d67ba9e55a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-17 17:45:59 -06:00
Ross Thompson
00218d559f Missing a file. Last commit will fail. 2022-11-17 17:45:41 -06:00
Ross Thompson
47e1d1764b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-17 17:38:52 -06:00
Ross Thompson
0106777f02 Finally have the correct replacement policy implementation. 2022-11-17 17:36:37 -06:00
Ross Thompson
70d7fca750 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
6ad9ba1e73 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-16 15:39:17 -06:00
Ross Thompson
faa13a96e0 I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps. 2022-11-16 15:38:37 -06:00
Ross Thompson
22ad49eef2 Progress on the cache replacement policy implementation. 2022-11-16 15:35:34 -06:00
Ross Thompson
847af7b95c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-16 12:44:06 -06:00
Ross Thompson
0796cd92fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-16 12:42:29 -06:00
Ross Thompson
42111db671 Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. 2022-11-16 12:36:58 -06:00
David Harris
59335ac70f comment cleanup 2022-11-16 10:23:20 -08:00
David Harris
be9c618c94 Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
128cc86254 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
Ross Thompson
1f21a2bab1 Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out. 2022-11-16 11:15:34 -06:00
Ross Thompson
e24378db8f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-15 14:49:32 -06:00
cturek
ffd03e9548 Attempt to fix FPGA synth errors 2022-11-15 20:34:28 +00:00
cturek
98b66aab9f Fixed lint errors in postprocessing 2022-11-15 20:31:23 +00:00
Ross Thompson
cf00f85456 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
62d28d8cca Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-15 10:18:56 -06:00
Ross Thompson
3df51716b1 Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state. 2022-11-14 16:02:20 -06:00
Ross Thompson
b53f8eceef Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
284b97aff6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 13:48:56 -06:00
David Harris
6372139af4 Removed comment about nonexistent possible bug 2022-11-14 09:56:33 -08:00
David Harris
06dbed92c8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 09:52:24 -08:00
David Harris
f9202187ba Removed comment about nonexistent possible bug 2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18 Updated wave file. 2022-11-13 21:34:45 -06:00
cturek
abaa33b92a Added majority of combinational logic 2022-11-14 00:06:38 +00:00
cturek
6740d77b63 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
12e3646153 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
f10700e666 Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
Ross Thompson
9d7ba19fe1 Changed IMWriteDataM to IHWriteDataM. 2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
hazard was not a straight forward merge.  I changed the way the LSU and IFU generate IFUStallF and LSUStallM.  They need to be suppressed by TrapM now.
 2022-11-13 12:25:22 -06:00
David Harris
84c4558641 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
879e62912b HPTW cleanup 2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68 Comments about division hazards 2022-11-13 04:17:37 -08:00
Ross Thompson
cc80f1f7b2 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
54544ae251 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
cturek
4a8661649c Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3 Fixed name change in hptw. 2022-11-10 16:13:31 -06:00
Ross Thompson
d912981ec9 Wavefile update. 2022-11-10 15:48:06 -06:00
Ross Thompson
40367eaf45 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-10 15:46:25 -06:00